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'P'P'P'P'P'P'P'P9,AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYxx||000000buffer_read_memoryperror_memorygeneric_print_addressgeneric_symbol_at_addressgeneric_symbol_is_validdisassemblerdisassembler_usagedisassemble_init_for_targetdisassemble_free_targetremove_whitespace_and_extra_commasdisassembler_options_cmpopcodes_assertdisassemble_set_printfinit_disassemble_infoaarch64_ins_noneaarch64_ins_regnoaarch64_ins_reglaneaarch64_ins_reglistaarch64_ins_ldst_reglistaarch64_ins_ldst_reglist_raarch64_ins_lut_reglistaarch64_ins_ldst_elemlistaarch64_ins_advsimd_imm_shiftaarch64_ins_immaarch64_ins_imm_halfaarch64_ins_advsimd_imm_modifiedaarch64_ins_fpimmaarch64_ins_imm_rotate1aarch64_ins_imm_rotate2aarch64_ins_fbitsaarch64_ins_aimmaarch64_ins_limmaarch64_ins_inv_limmaarch64_ins_ftaarch64_ins_addr_simpleaarch64_ins_addr_regoffaarch64_ins_addr_offsetaarch64_ins_rcpc3_addr_offsetaarch64_ins_addr_simmaarch64_ins_rcpc3_addr_opt_offsetaarch64_ins_addr_simm10aarch64_ins_addr_uimm12aarch64_ins_simd_addr_postaarch64_ins_condaarch64_ins_sysregaarch64_ins_pstatefieldaarch64_ins_sysins_opaarch64_ins_barrieraarch64_ins_barrier_dsb_nxsaarch64_ins_prfopaarch64_ins_hintaarch64_ins_reg_extendedaarch64_ins_reg_shiftedaarch64_ins_reg_lsl_shiftedaarch64_ins_sve_addr_ri_s4xvlaarch64_ins_sve_addr_ri_s6xvlaarch64_ins_sve_addr_ri_s9xvlaarch64_ins_sve_addr_ri_s4aarch64_ins_sve_addr_ri_u6aarch64_ins_sve_addr_rr_lslaarch64_ins_sve_addr_rz_xtwaarch64_ins_sve_addr_zi_u5aarch64_ins_sve_addr_zz_lslaarch64_ins_sve_addr_zz_sxtwaarch64_ins_sve_addr_zz_uxtwaarch64_ins_sve_aimmaarch64_ins_sve_aligned_reglistaarch64_ins_sve_asimmaarch64_ins_sve_indexaarch64_ins_sve_limm_movaarch64_ins_sve_quad_indexaarch64_ins_sve_reglistaarch64_ins_sve_strided_reglistaarch64_ins_sve_scaleaarch64_ins_sve_shlimmaarch64_ins_sve_shrimmaarch64_ins_sve_float_half_oneaarch64_ins_sve_float_half_twoaarch64_ins_sve_float_zero_oneaarch64_ins_sme_za_vrs1aarch64_ins_sme_za_vrs2aarch64_ins_sme_za_tile_to_vecaarch64_ins_sme_za_hv_tilesaarch64_ins_sme_za_hv_tiles_rangeaarch64_ins_sme_za_listaarch64_ins_sme_za_arrayaarch64_ins_sme_addr_ri_u4xvlaarch64_ins_sme_sm_zaaarch64_ins_sme_pred_reg_with_indexaarch64_ins_x0_to_x30aarch64_ins_simple_indexaarch64_ins_plain_shrimmaarch64_opcode_encodeextract_fieldsaarch64_ext_noneaarch64_ext_regnoaarch64_ext_regno_pairaarch64_ext_regrt_sysinsaarch64_ext_reglaneaarch64_ext_reglistaarch64_ext_ldst_reglistaarch64_ext_ldst_reglist_raarch64_ext_lut_reglistaarch64_ext_ldst_elemlistaarch64_ext_advsimd_imm_shiftaarch64_ext_shll_immaarch64_ext_immaarch64_ext_imm_halfaarch64_ext_advsimd_imm_modifiedaarch64_ext_fpimmaarch64_ext_imm_rotate1aarch64_ext_imm_rotate2aarch64_ext_fbitsaarch64_ext_aimmaarch64_ext_limmaarch64_ext_inv_limmaarch64_ext_ftaarch64_ext_addr_simpleaarch64_ext_rcpc3_addr_opt_offsetaarch64_ext_rcpc3_addr_offsetaarch64_ext_addr_offsetaarch64_ext_addr_regoffaarch64_ext_addr_simmaarch64_ext_addr_uimm12aarch64_ext_addr_simm10aarch64_ext_simd_addr_postaarch64_ext_condaarch64_ext_sysregaarch64_ext_pstatefieldaarch64_ext_sysins_opaarch64_ext_barrieraarch64_ext_barrier_dsb_nxsaarch64_ext_prfopaarch64_ext_hintaarch64_ext_reg_extendedaarch64_ext_reg_shiftedaarch64_ext_reg_lsl_shiftedaarch64_ext_sve_addr_ri_s4xvlaarch64_ext_sve_addr_ri_s6xvlaarch64_ext_sve_addr_ri_s9xvlaarch64_ext_sve_addr_ri_s4aarch64_ext_sve_addr_ri_u6aarch64_ext_sve_addr_rr_lslaarch64_ext_sve_addr_rz_xtwaarch64_ext_sve_addr_zi_u5aarch64_ext_sve_addr_zz_lslaarch64_ext_sve_addr_zz_sxtwaarch64_ext_sve_addr_zz_uxtwaarch64_ext_sve_aimmaarch64_ext_sve_aligned_reglistaarch64_ext_sve_asimmaarch64_ext_sve_float_half_oneaarch64_ext_sve_float_half_twoaarch64_ext_sve_float_zero_oneaarch64_ext_sme_za_tile_to_vecaarch64_ext_sme_za_hv_tilesaarch64_ext_sme_za_hv_tiles_rangeaarch64_ext_sme_za_listaarch64_ext_sme_za_arrayaarch64_ext_sme_za_vrs1aarch64_ext_sme_za_vrs2aarch64_ext_sme_addr_ri_u4xvlaarch64_ext_sme_sm_zaaarch64_ext_sme_pred_reg_with_indexaarch64_ext_sve_indexaarch64_ext_sve_limm_movaarch64_ext_sve_quad_indexaarch64_ext_sve_reglistaarch64_ext_sve_reglist_ztaarch64_ext_sve_strided_reglistaarch64_ext_sve_scaleaarch64_ext_sve_shlimmaarch64_ext_sve_shrimmaarch64_ext_x0_to_x30aarch64_ext_simple_indexaarch64_ext_plain_shrimmaarch64_decode_insnaarch64_symbol_is_validprint_insn_aarch64print_aarch64_disassembler_optionsfieldsaarch64_sve_pattern_arrayaarch64_sve_prfop_arrayaarch64_rprfmop_arrayaarch64_sme_vlxn_arrayaarch64_brbop_arrayaarch64_get_qualifier_esizeaarch64_select_operand_for_sizeq_field_codingaarch64_get_operand_classaarch64_get_operand_nameaarch64_get_operand_descaarch64_condsget_cond_from_valueget_inverted_condaarch64_operand_modifiersaarch64_get_operand_modifieraarch64_get_operand_modifier_valueaarch64_get_operand_modifier_from_valueaarch64_extend_operator_paarch64_barrier_optionsaarch64_barrier_dsb_nxs_optionsaarch64_hint_optionsaarch64_prfopsaarch64_stack_pointer_paarch64_zero_register_paarch64_g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0 0 0 644 2680 ` ELF8@@ { @@O@O@ *# @\@O@  @X@@!O@ | @X@@?#T @X@@ @?CT @X@@!#@ @?#T @|@T @|@@?T@#@! @|@?iTR  @T@@ @@R{Ũ_{//@q`T@@@@/@`? @@@@@`? {è_{ @@ @@@`? {¨_CC_C RC_Unknown error %d Address 0x%lx is out of bounds. 0x%08lxGCC: (crosstool-NG 1.28.0) 15.2.0zRx 4AP K8xA0\X@A NxADAD 4$+4x9@Oidis-buf.c$x$dbuffer_read_memorymemcpyperror_memorygeneric_print_addressgeneric_symbol_at_addressgeneric_symbol_is_valid$ hl@@<4\|.symtab.strtab.shstrtab.rela.text.data.bss.rodata.comment.note.GNU-stack.rela.eh_frame @@ &\,\1`H90#BWR@Xx x  (adisassemble.o/ 0 0 0 644 4512 ` ELF`@@ o9 @xqT@<q!To@9qT@_{@@ {¨_C@T@$@xqT<q!T@!P@!R`9@!R 9@!P@!R`9@!R 9  C_C@ C_{@aT҂@@@ @9*!|@xaxqT@@ @9qT@@ 9@@AT @@ @9*!|@xaxqT@@ R9@@@ @9qT@3@@9qT@@9qT@@?aT@@@@9q@T@@@?T@@@@@@ @@ 9@@@9qaT@@9q`T@{Ĩ_@@99@9qAT9@@9{9{@9qAT{9@9qT@9{@9 K@9{@9?kT@9{@9 K_{@@ @ @@@@@ _assertion fail %s:%dPlease report this bugGCC: (crosstool-NG 1.28.0) 15.2.0zRx A0^0(A HPAdhAE,A@A c4A DA O"5H^(q@\,6=JRk4zPDdisassemble.c$x$ddisassemblerprint_insn_aarch64print_insn_big_armprint_insn_little_armdisassembler_usageprint_aarch64_disassembler_optionsprint_arm_disassembler_optionsdisassemble_init_for_targetaarch64_symbol_is_validarm_symbol_is_validdisassemble_free_targetremove_whitespace_and_extra_commasstrlen_sch_istablememmovedisassembler_options_cmpopcodes_assert_bfd_error_handlerabortdisassemble_set_printf, 0 LP\`,0 48<@DHL4Tl@\P.symtab.strtab.shstrtab.rela.text.data.bss.rodata.comment.note.GNU-stack.rela.eh_frame @@ p &,1/90#B*W0R@8     adis-init.o/ 0 0 0 644 2112 ` ELF@@@ { "R@@ @$@AR0@0@@4@!R@@@ @@@@!@@!D@!H@!L@!P@AR@ 9 {è_GCC: (crosstool-NG 1.28.0) 15.2.0zRx  A0{ (/BPfdis-init.c$x$dinit_disassemble_infomemsetbuffer_read_memoryperror_memorygeneric_print_addressgeneric_symbol_at_addressgeneric_symbol_is_valid$     .symtab.strtab.shstrtab.rela.text.data.bss.comment.note.GNU-stack.rela.eh_frame @@ &4,4104#:WOX8J@   (Yaarch64-asm.o/ 0 0 0 644 54512 ` ELF@@ C@D@XC_C@D@ C_C@@C_C@@ CC_C@@(JC_C@@,KC_C@@|S C_{@@~ @q!T5R@@~ @*} @{¨_C@!R QC_@} @qkT@q T@@! @@?kmTR @@@! @@@ R_{@@|q T@@qT@@q T@@@@ q-Tb>R@@*@ @@@ @ *@ @@@!*@ {è_{ '##@ *'@ '@@'@3$@@` ??@ @{Ĩ_{/+/@} @+@@ {è_{@} @@{¨_{/@ @qaT/@$@qT R/ FR/@{è_{@$@ qT R/@ @ qaT/ BIR/@{è_{/+@ @qT@@9+@$@qT@@9//@+@?kT/@q!TKR+@qT/@xS+@?kaT RR{è_{@qKT@qT@qT@q-TBOR~|@@  ~|@@  @~|@@  {¨_{@@@q)TBQR@Q* h`8q!TQR@Q* h`8{è_{osw{===#='=+=/=3=C;?;@@?qT,!} " ;;@_qT,!}@ |@@@OO@qT"R;@@?qT,!} " ;;@_qT,!}@ |@@@KK@} #@@@K@#@@@ $O@QOqT  {Ш_{'#R?@?@~ @qT@?@~ @;R#@@;@;@} @#@ $#?@Q?'@?kT  {Ĩ_{@@R@{è_  R_{ '##@@'@`K_'@@_@R*@F R @{ƨ_{@@@@@@ @**@*/@@@\qT@@@(qaT@@9QS@@qT@@ @q!T@@q TR@ @S@ ORO@@R @ @@S@ KRK@@R@@@qT@ @W@@9(q T(qkT,QqTW@ q)TRRRCRRW@@W@q)TBRRR$RcRRW@@R@@@qT@ @[[@ q)TRR[@@Rh@ @_@@@DqT_@xS_@@9 qT q TqTq, TqTqTL_@<q)TRRDRCRR_@@i;_@q)TbRRR$RcRR_@@U'_@ q)TRRRCRR_@@B_@q)TRR_@@R<R R{ƨ_{@@@@@9R*@*&@D@9QR*@R R{Ĩ_{O@@-K@@@9R*@ RK@qTK@qhTK@ q`TK@ qTK@qTK@qT.@D@9qTqT qT qLTqTqT RO @RO RO@ROR@D@9qT`RO ROROORRO@@R R{Ũ_{@@qK@@@9R*@ ROK@qT@D@9qaT RORO@@`R R{Ũ_{@@@@@9R*@* R{Ĩ_{CGOK@@q!TB(R@@@9R*@ Re@@9 qT qTqTq,TqTqT@ @OK@ @xSO RK@ @tSO@RK @ @pS2O@RKRfReRdRcRRO@@&BR!R@RRK@@ R{Ũ_{@@9O@@@8qTO@G@@ @*G@@`RO@|SO@@qT@@q T0R@@qATO@R *@@ KK @@*O@R @ KRRCRRK@@ R{Ũ_{@@'@qT'@B'@qT'@C'@qT'@D''@*@@= R{Ũ_{@@@@@@ @DR*@ R R{Ĩ_{@p@9O9@@/@8@O@ @WCG@`@9qTOA9 qT/@|@//@q*Tb;R/@%RRCRR*@NO@qaT RPO@qTO@q Tbfields[n] != FLD_NILfield->width < 32 && field->width >= 1 && field->lsb >= 0 && field->lsb + field->width <= 320dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM && src < AARCH64_MAX_OPND_NUMls[size - 1] != (unsigned char)-1/export/home/pmunts/src/muntsos/toolchain/crosstool/build.d/aarch64-muntsos-linux-gnu/src/gdb/opcodes/aarch64-asm.cnum <= 5info->idx == 1reglane_index < 4reglane_index < 8reglane_index < 16reglane_index < 2info->reglist.has_indexinfo->type == AARCH64_OPND_IMM_VLSR || info->type == AARCH64_OPND_IMM_VLSL(int)imm >= 0kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSLesize == 4 || esize == 2 || esize == 1rot < 2Urot < 4Uinfo->idx == 0info->addr.preind == 1 && info->addr.postind == 0inst->opcode->iclass != ldst_unscaled && inst->opcode->iclass != ldstnapair_offs && inst->opcode->iclass != ldstpair_off && inst->opcode->iclass != ldst_unprivinfo->addr.preind != info->addr.postindspecified register cannot be read fromspecified register cannot be written toinfo->reglane.regno < (1U << reg_bits)(val & mask) == valinfo->idx > 0info->idx >= (int)opnd_backshiftimm % range_size == 0 && (imm / range_size) < max_valuefld_zan_imm < (range_size == 4 && ebytes < 8 ? 4 : 8)imm % (countm1 + 1) == 0info->reg.regno <= 30qualifier == AARCH64_OPND_QLF_V_4S || qualifier == AARCH64_OPND_QLF_V_2Dinst->operands[0].qualifier == AARCH64_OPND_QLF_S_Squalifier >= AARCH64_OPND_QLF_S_B && qualifier <= AARCH64_OPND_QLF_S_Qaarch64_get_operand_class (inst->opcode->operands[0]) == AARCH64_OPND_CLASS_SIMD_REG && qualifier >= AARCH64_OPND_QLF_V_8B && qualifier <= AARCH64_OPND_QLF_V_2Dnum >= 0 && num <= 3(value >> 1) == value1idx == 0 || idx == 1aarch64_get_operand_class (inst->opcode->operands[idx]) == AARCH64_OPND_CLASS_INT_REGaarch64_get_operand_class (inst->opcode->operands[0]) == AARCH64_OPND_CLASS_INT_REGinst->opcode == NULL || inst->opcode == opcodeopcode->operands[i] == inst->operands[i].typeinsert_field_2aarch64_ins_reglaneinsert_fieldsaarch64_ins_ldst_elemlistaarch64_ins_advsimd_imm_shiftaarch64_ins_advsimd_imm_modifiedaarch64_ins_imm_rotate1aarch64_ins_imm_rotate2aarch64_ins_ftaarch64_ins_addr_offsetaarch64_ins_addr_simmget_logszaarch64_ins_addr_simm10aarch64_ins_sve_quad_indexaarch64_ins_sve_strided_reglistaarch64_ins_sve_shlimmaarch64_ins_sve_shrimmaarch64_ins_sme_za_hv_tiles_rangeaarch64_ins_sme_za_arrayaarch64_ins_x0_to_x30get_operand_field_widthencode_asimd_fcvtencode_asisd_fcvtxndo_special_encodingselect_operand_for_sf_field_codingselect_operand_for_fptype_field_codingselect_operand_for_scalar_size_field_codingcopy_operand_infoaarch64_opcode_encodeGCC: (crosstool-NG 1.28.0) 15.2.0zRx  AF04AKH AF`$AGx$AG$AG AFA ` AFA0dA0y 0`A@BTTHA0Pt<A M|A0]tA0[A0sA yA0f4A jTA@nt0A0J$A0G dA` B U0A`  lA@YtAP [0AP ePLA@QpAP _4AP KAP k`A@V8A` @A@N0AP kPAP jpXA@T|AP ]A` p\A@UDA@O\AP U0DA@OP$AP GpAP ~tAP [AP lpAP Z(AP HAP b0A@`PHA@PphA`A WxA@\`A@VHA@PTAP SHA@P0PA@RPAP lpA@^`A@VAP ^AP ^AP `AP `0AP `PpA@ZpA@kAP `A0`<A@M<A@M <A@M0 A@rP hAP Xp @A@N AP b @A@N AP f LA@Q AP t0 `A@VP AP op A` u pA@Z pA@Z lA@Y A` _ xA` \0 AP oP A` tp A` p PAP R AP t xAP \ AP ^ A` t0 |A@]P |AP ]p tAP [ A0z A0_ A0` A0u  A@B4 A0~ T HA` B  x A@B9 8A L ,AI 8AL (A H PA R$A `<A0p\A _tPA RxA \A0}DA OA0mAAXW - 4FT [t$u$$   @4,`DHQ<_|8 #t` ' ,) ?I ``n  0 ( H ! p " 9L c z  - ( H ` x "3 J `Cr D hEEFIJH R>W8RW,f(X8x`X(XPX`Y(ZZPZxt[p\D1\A We $$ d 0l$t!4L9S4q8`L8@ #x;(XM|^z\ Dd\D$ ( (t8 N T!pp !( " |# $H L$h %x ,&` &H! &T= ('HO p'P` 'y x( (` X) ) X* *" h+= +pY `,u - $.< `.< .< . /h 0@1 P0G 0@`  1{ 1L  2 2` D3 4 4p T5p5 5lT 06l 7x ,9 : < >P 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%s.byte 0x%02x.short 0x%04x.word The following AARCH64 specific disassembler options are supported for use with the -M switch (multiple options should be separated by commas): no-aliases Don't print instruction aliases. aliases Do print instruction aliases. no-notes Don't print instruction notes. notes Do print instruction notes. extract_fieldsaarch64_ext_regno_pairaarch64_ext_regrt_sysinsaarch64_ext_reglaneget_logszaarch64_ext_ldst_reglist_raarch64_ext_ldst_elemlistaarch64_ext_advsimd_imm_shiftget_operand_fields_widthsign_extendaarch64_ext_advsimd_imm_modifiedaarch64_ext_imm_rotate1aarch64_ext_imm_rotate2aarch64_ext_rcpc3_addr_opt_offsetaarch64_ext_reg_extendedget_operand_field_widthdo_special_decodingselect_operand_for_sf_field_codingselect_operand_for_fptype_field_codingselect_operand_for_scalar_size_field_codingcopy_operand_inforeset_operand_qualifierconvert_bfm_to_bfcconvert_movebitmask_to_movdetermine_disassembling_preferenceaarch64_opcode_decodeget_style_textaarch64_apply_styleremove_dot_suffixprint_verifier_notesprint_insn_aarch64_word_undefinedunpredictableNYIGCC: (crosstool-NG 1.28.0) 15.2.0zRx <A M8(AHPADh<AM AF$AG$AG AF4AK$AG$AG($AG@$AGX$AGp AFA `A0pA _ AFA0d `A@BT<<A M\|A0]|tA0[A0sA yA0fACA z4A0lTA"!ntA0p(A HA0^TA0SlA0YTA0S4A0bT$A0G l\AP BSAP uA@i$AP GxA@\XAT0AP wPlA@Yp8AP A` {AP h `A` B TlA@YA` 4PA@RTAP gtAP fPA@RAP dA0AP a tA@[,tAP [LDA@OlAAP lAP {TAP SAP p AP o,AP ~ LDA` B MpPAP RA@pAP EAP bTA@S XAP T0 TA@SP AP op AP C AP p lA@Y A0w hAP X hAP X0 pAP Z P A@Bit \AP U TAP S (AP H A@C TAP S A0E4 <A@MT <A@Mt <A@M Am A@a AP ` A@a pA@Z, pA@ZL lA@Yl AP ~ A` r `A` V LAP Q AP { A` i, A` fL AP el AP d A` _ AP k AP c AP ^ lA@Y,hA@XLAP klAP sHAPA@dA@dXA@TxAP \$pAP ZDA0hdA0^|A@qA0phA0XA0i A@B  A` @PA R`4AKxdA W<AMA@aA@kA@DA0g A ^@A b`A0xA0yA _AAPO4 A0KA@ TAS8A@^XA0B$xAB @AA>= A0vA0kA0y$A sDAP odAAPOA0lDA0OAP cAgAlA e<<(/d@|<T c$t$  @4t$$$$ $;( UXHp @   <` 4<p|>@ #Ut|h '` ,4    U-U7HY k(v0 p <  (#, /` F TdllT     * Ap !X o % " =(?CD%,YH1[U\u ]^_h``Pd ( lnPn4nd*To<=oPpcpv qr sst pu$vG( #^؂ty4 P ܅T@H@h  x " l@1 C  Y m @{ ,    ē   0 D ܗ p* U  9 @ H V n     |    P$ t\- D ] x X$ |x X L 0l 8 $ 9 p`I l^ <  #P `# $ $P $ ( 4)t )t +D1 `+S d w d- . /T  d0,2233DNj45P{5L6h7 !7K8T_wL9X9T9:;+<lG=heP>h>p?\8@T@(ABT*8D<FtD<cD<E4FFHGpGp (Hl(HGJcdL`MLNOPPRRS>UTUmPVVlEF ILUV VXY4 >T (?x ? 8@ @ A B C8 8DX tDx D D E 4F F HG0 GP (Hp H J dL M N O0 PP PRp R S U U PVV00#G\8W@8/ @p  >faarch64-opc.o/ 0 0 0 644 990856 ` ELF@@ @ @9q`TR@@qmT R_C@D@`T@D@L@@?@T@D@L@@*?aT RR @D@L@@*?C_C@D@OC_C@D@XC_C@D@dC_C@@ CC_C@@0LC_C@@DC_C@@|S C_{@@~ @q!T5R@@~ @*} @{¨_{/+/@/@|@~ @*} @*+@ +@/~ @qT+@qT+@|q)T7R+@{è_C@| C_{@@@q)TBQR@Q* h`8q!TQR@Q* h`8{è_C?9?@94qT?@9\qhT RRC_C?9?@9qT?@9$qhT RRC_{ @@9qT@@9@@9?k!T@@9q T@@9@@9kT@@9@@9kaT Rd@@9qT@@9qT@@9*@@9xSkaT@RG@@9@@9?kT@@9qT@@9q T@@9*@@9xSkT@@9@@9k!T`R@@9qqT@@9ZqT@@9qaTRR @{è_{@c** h`8{¨_C@|@@C_C@|@@C_C@|@@C_{@<q)TRh e c3@q)T3@qbT3@q(T3@|q"T3@pq#T3@pq'T3@@qh'T3@<qT3@q T3@qH&T3@q`T3@q%T3@q`T3@q$T3@qh$T3@qT3@qT3@qH#T3@q"T3@qT3@qT3@q@T 3@|I{93@|!@!R Q{B9@ K!R Q*R*R7@@S@RqTR3@R{9'RRRR7@@S@Rq`TR3@< {9gRRRR7@@S@RqTRS@@9{9{B9R Q*RRR7@@S@RqTRS@@9{9{B9R Q*RRR7@@S@RqTR3@!R{9{B9!R Q*RRR7@@S@iRqTR|3@Q{9{B9!R Q*RRR7@@S@MRq TR`3@Q{9{B9!R Q*RRR7@@S@1Rq@TRDS@@<qTRR7@@ R7S@@9{9{B9R Q|@gg@*@q*R%R*R7@@S@RqTR             3@(q@T3@(q(T3@$q`T3@$qhT3@qT3@qbT3@qHT3@qT3@q@T3@q(T3@qT3@qT3@q T3@q` Tl3@|!@$R*7@@S@Rq`TRS@@@9@@A|Kq` T7@@R3@|!@R@ **7@@S@Rq`TRS@H@9Q2S@@@9*@ * qT7@@QR{@N@$R*7@@S@RqTRi e c a3@dqT3@dq(?T3@`q`T3@`qh>T3@\q>T3@XqT3@TqT3@Tq<T3@Pq`T3@Pq(<T3@LqT3@Lqh;T3@HqT3@Hq:T3@ q4T3@ q9T3@q`T3@q(9T3@q@3T3@qh8T3@qT3@q7T3@q,T3@q6T3@q6T3@|q-T3@xq'T3@xqh5T3@tq$T3@tq4T3@pq` T3@pq3T3@lqT3@lq(3T3@dq@T3@hqTS@@9{9{B9R Q|@gg@*@*@**%R*R7@@S@xRq@.TR@*@**%RRR7@@S@aRq+TR@*@**%RRR7@@S@JRq)TR@w*@|**R$RR7@@S@3Rq`&TR@`*@e**ERdRR7@@S@Rq#TRv@I*@N**RdRR7@@S@Rq !TR_@2*@7**ERRR7@@S@RqTRH@*@ **ERRR7@@S@RqTR1@*@ **ERdRR7@@S@Rq@TR@*@**ER$RR7@@S@RqTR@*@**ERRR7@@S@RqTR@*@**RdRR7@@S@{Rq`TR@*@**R$RR7@@S@dRqTR@*@**%RRR7@@S@MRq TR@z*@**RRR7@@S@6Rq TRS@@9{9@_R@!{B9 *gg@Tg@gg@*@Mq*R@*R7@@S@ Rq@TRd ` ^ \ Z X V T R P N L J H F D B3@0QqTS@@qTRR7@@R2S@@q)T3@V qTRR7@@R   3@\q!T7~|@@ @8qT7@@ @@q Tq(TqTq Tqh TqTq TqBTqTq( Tq@Tq Tq`Tq( TLqTTqTTS@p@9q T7@@R S@p@9q TS@p@9q! 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S@W@G@@@*S@W@}?@@9qT@@9qT@@9@#@@*@@@@A@@T@@T@@@@ @(@@9qT@@9qT@A @@9qT@8S@W@@@@`@y<q`TR R@@9qT@@9qT@@9**@@@*@@@@@@T@@T@@@@ @S@W@q@@qT@bS@W@^@@@@9*@P@@*@H@@@nS@W@:@@@)T4R@xa@~S@W@@@@)T5R@xa@bS@W@@@@S@W@@@@S@W@@@@"C`@S@W@@*K@nqT@@K@* T@@@|)T>R@xaT@xa@S@W@@@@S@W@@*K@/qT@@9qT@@K@J*렮T@@@|)T@R@@xaT@@xa@`S@W@@@@S@W@@@9qTW@@8@*| @W@@3S@@4@@@ @@V@@@<)T"CR@xaT@xa@S@W@@@@%S@W@G@@9qT qT,@@@@ S@W@@@@@@@S@W@@@@@S@W@ ո@S@W@@ @T@@@@@ @@S@W@@@@S@W@~@ @T@8@qT@8@qT@@@S@W@d@@@@8@*| @@@ @@tS@W@@@ @T@@@`@@ @@SS@W@@@@CS@W@G@@9 qT q,TqTqT<@@*@R@"C`@"S@W@.@@*R@"C`@S@W@@@*R|__@C`@S@W@S@W@ @*K@[qT@@K@}*uT@@*@S@W@@@@@S@W@R R?4@T@?AqT@@%@@&@@@@@?Axa@@$@@%@@?Axa?A??A@?kkT@@?AxaTQO@t@!@s?@T?@!R;@T;@s@s@@S@W@8@@O@s?@T?@!R;@T;@s@s@@S@W@@@!Ri@@qaT@@qT@@@@*@S@W@@@@@*@S@W@@@S@W@@@!R,@;@@S@W@w@@*@@9**K@@R@@S@W@b@@!R@@*@@9**1@@S@W@M@@!R@@S@W@@@*@@9**@@S@W@@@*@@9**@@*@@9**@@S@W@q@@!R@@qT@@b@@*@S@W@U@@OS@W@K??A{ {{@ @q@T{@ @@@! @@?k!T@ {@@ AT@ {@ @ aT RR9C99?A{ @@@?k T?A{ @Rq T?A{ @RqT@TC9qT?A{ @C9qT@`T@(?A{ @qT@!?A{ @qT@!?A??A{ @T @`T@@S@W@@@@|S@| S@|S @|S @*****@S@W@?!?A{ @@@?kT?A{ @@qT@@@ J qT ?A??A{ @!T ?A{ @!ToR?A{ @@FS@W@B@@@@9S@W@5@@@@9qT@@@@TS@W@"@@@@uS@W@@*K@RqT@@@K@k T@@@*@'S@W@@@@T@@@@CS@W@@@@*@S@W@@@@T@xaT@xa@S@W@@@@S@W@@S@W@@S@W@@S@W@@@@*@S@W@w@p@@*@@S@W@]@VS@W@R@S@W@G@@@qT@@@@S@W@3@@RARe@)S@W@%@@RARV@S@W@S@W@           {BSC[DcE3@_C@C_C@GC_C@FC_@ @qaT R @ @@ AT@ @ @ aT RR_C@ @BC_{'@tT R@''@ T'@qaTR'@qaT R@ @@ AT@ @@ aT RR{Ũ_'9 '@?'@|S;'@| S7'@ qT?@;@?kT7@;@?kT;@|q`T R '@ qT?@7@?kaT RR_{79`RK@@!T©R@@(@q T⩂R@9qT@@O7@OO@q!T"RR#RBRRO@*K@kaT RR{Ũ_'9 @(@?@x@;@@7?@;@?k T?@7@?kT;@7@?kT @R @! @ RR_{ @@ @@ @#|@}}}A@I {¨_{ / @@T @@ @@ T@@@q`T R/@ T@@@qaT@R/ @ @/@ /@q@T/I @ @@ {è__9@@@@T@@@@|@}}} @@T@@@qT@@@? T@aR@@@@@@@@@@ @!R9R{@@qT_@9qAT@T@@@?T@AR@@@@@@@@ @!R9RS7M@7! xaqT@7! xaqT@7! xaqT@7~|@(@@7~|`(@_kT@R@7! xaqT@!@7! xaqT@!@!@7@@!R9R7@77@qMT R_{79@!TbR@@!TR@@@@qT@@aTR/@!TBR@D@a T@@T@R@!@@!R9R@@A@9RqT@aT RR_9_F9_9@@_F9@Rq`TR@@ qT@@@;T@@@_F9qTAqT@R@!@@!R9R@A@@q@5T@ @`T@ @@dT@ @@|T@ @@_!T@R@!@@!R9R@@q!T@R@!@@!R9Rp@@`;=<===> =?==== ==C R R9C@q T̂R@@h@q!T R9@@C;=<===> =?==== ==9@j@ᯁ~|@@ ;=<===> =?==== ==3A,qT,qh TqTqTq`TqhTq(TqT`qT\q"Tq@TqTqTqTq(TqTqTqhTtqTlqT&|QqhTCAS@?kTAAD99F9F9?kTF99;=<===> =?==== ==A  AAA?kTF9q!TBӂR@`;=<===> =?==== ==@@qTD99F99F9q`TAq*T@R@!@@!R9RC9dq T@R@!@A@!R9Ru@@?k T@R@!@A@!R9Ra@qT@R RAqT@R@!@@!R9RDS@CA?kT@R@!@@!R9R1AA?k-T@R@!@A@!R9RD9q@TA9qTA9F9?k T@R@!@@!R9R @@@ @?kT@@@A{ܨ_@@tS! @tS @ @  T@ @ @?`TR<@qT@*@`?kT@|@@q T@<@P<?k!T@<<@@qT@@H?kaTR@@T@ H@T@mT RR_@@ @`T @ @@ @@ AT@ @@ @@ `TR"@@@ qT@p@9 qT @ D`TR@@@$qT@p@9 qT @ C`TR R_? @/export/home/pmunts/src/muntsos/toolchain/crosstool/build.d/aarch64-muntsos-linux-gnu/src/gdb/opcodes/aarch64-opc.hoperand->fields[n] != FLD_NILwidth > 0 && width < 320ls[size - 1] != (unsigned char)-1pow2vl1vl2vl3vl4vl5vl6vl7vl8vl16vl32vl64vl128vl256mul4mul3allpldl1keeppldl1strmpldl2keeppldl2strmpldl3keeppldl3strmpstl1keeppstl1strmpstl2keeppstl2strmpstl3keeppstl3strmpldkeeppstkeeppldstrmpststrmvlx2vlx4iallinj                                               eqnoneneanycshsnlastccloullastmifirstplnfrstvsvchipmorelsplastgetcontlttstopgtlealnv /export/home/pmunts/src/muntsos/toolchain/crosstool/build.d/aarch64-muntsos-linux-gnu/src/gdb/opcodes/aarch64-opc.cvalue < 16mslrorasrlsrlsluxtbuxthuxtwuxtxsxtbsxthsxtwsxtxmulmul vl#0x00oshldoshstosh#0x04nshldnshstnsh#0x08ishldishstish#0x0cldstsy oshnxsnshnxsishnxssynxs csyncdsynccjjc "$&pldslckeeppldslcstrmplil1keepplil1strmplil2keepplil2strmplil3keepplil3strmplislckeepplislcstrmpstslckeeppstslcstrm width < 32((enum aarch64_opnd) qseq_list[0][known_idx]) == AARCH64_OPND_NILNILwxwspspbhsdq2b4b2h8b16b4h8h2s4s1d2d1qzmtagCRimm_0_7imm_0_15imm_0_31imm_0_63imm_1_32imm_1_64retrievingoperand_variant_qualifier_p (qualifier)qualifier_value_in_range_constraint_p (qualifier)i >= 0 && i <= AARCH64_MAX_OPND_NUMnb_imms == TOTAL_IMM_NBimmediate valueimmediate offsetregister numberregister element indexshift amountmultipliersize < 63expected a selection register in the range w12-w15expected a selection register in the range w8-w11range_size == 2 || range_size == 4starting offset is not a multiple of 2starting offset is not a multiple of 4expected a single offset rather than a rangeexpected a range of two offsetsexpected a range of four offsetsopcode->operands[idx] == opnd->type && opnd->type == typesecond reg in pair should be xzr if first is xzridx == 1 || idx == 2 || idx == 3 || idx == 5reg pair must start from even regreg pair must be contiguousidx == 1 && (aarch64_get_operand_class (opnds[0].type) == AARCH64_OPND_CLASS_SYSTEM)extraneous registermissing registerstack pointer register expectedpnstart register out of rangepunexpected address writebackaddress writeback expectedopnd->addr.writeback == 0negative or unaligned offset expectedidx == 1invalid register offsetinvalid post-increment amountinvalid shift amountinvalid extend/shift operator!opnd->addr.offset.is_regopnd->addr.preindinvalid addressing modeopnd->addr.offset.is_reg(aarch64_operands[type].flags & OPD_F_NO_ZR) == 0opnd->shifter.kind == AARCH64_MOD_LSLopnd->shifter.operator_present == 0index register xzr is not allowedinvalid increment amountnum >= 1 && num <= 4invalid shift operatorshift amount must be 0 or 12immediate out of rangeidx == 1 && opnds[0].type == AARCH64_OPND_Rdshift amount must be a multiple of 16negative immediate value not allowedsize < 32idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM && opnds[0].type == AARCH64_OPND_Rdimmediate zero expectedrotate expected to be 0, 90, 180 or 270rotate expected to be 90 or 270idx == 2shift is not permittedinvalid value for immediateshift amount must be 0 or 16floating-point immediate expectedno shift amount allowed for 8-bit constantsshift amount must be 0 or 8immediate too big for element sizeinvalid arithmetic immediateopnd->imm.is_fpfloating-point value must be 0.5 or 1.0floating-point value must be 0.5 or 2.0floating-point value must be 0.0 or 1.0invalid replicated MOV immediateopnd->shifter.kind == AARCH64_MOD_MULbyte index must be a multiple of 8aarch64_pstatefields[i].nameidx == 0 && opnds[1].type == AARCH64_OPND_UIMM4the register-index form of PRFM does not accept opcodes in the range 24-31vaarch64_get_qualifier_nelem (qualifier) == 1idx == 1 || idx == 2extend operator expectedmissing extend operator'LSL' operator not allowedopnd->shifter.operator_present || opnd->shifter.kind == AARCH64_MOD_LSLW register expectedshift operator expected'ROR' operator not allowedinst->operands[0].type == AARCH64_OPND_SME_ZA_array_off4inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVLaarch64_get_operand_class (inst->operands[i].type) == op_classw0w1w2w3w4w5w6w7w8w9w10w11w12w13w14w15w16w17w18w19w20w21w22w23w24w25w26w27w28w29w30x0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x15x16x17x18x19x20x21x22x23x24x25x26x27x28x29x30wzrxzrz0.sz1.sz2.sz3.sz4.sz5.sz6.sz7.sz8.sz9.sz10.sz11.sz12.sz13.sz14.sz15.sz16.sz17.sz18.sz19.sz20.sz21.sz22.sz23.sz24.sz25.sz26.sz27.sz28.sz29.sz30.sz31.sz0.dz1.dz2.dz3.dz4.dz5.dz6.dz7.dz8.dz9.dz10.dz11.dz12.dz13.dz14.dz15.dz16.dz17.dz18.dz19.dz20.dz21.dz22.dz23.dz24.dz25.dz26.dz27.dz28.dz29.dz30.dz31.dqualifier == AARCH64_OPND_QLF_S_S || qualifier == AARCH64_OPND_QLF_S_Dopnd->type != AARCH64_OPND_LEt || opnd->reglist.has_indexnum_regs >= 1 && num_regs <= 4%li[%s]%s%d{%s-%s}%s%s%d.%s{%s}%s{%s, %s}%s{%s, %s, %s}%s{%s, %s, %s, %s}%s[%s]!#%d[%s, %s]![%s], %sopnd->shifter.kind == AARCH64_MOD_MUL_VL[%s, %s, %s][%s, %s]#%li, %s %s, %s[%s, %s%s]{, %s}zaza0.hza1.hza0.sza1.sza2.sza3.sza0.dza1.dza2.dza3.dza4.dza5.dza6.dza7.dU"D @comment_size > 0comment_size == 0unpredictable encoding (Rt!=31): #%uopnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_Xopnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_WSP || opnd->qualifier == AARCH64_OPND_QLF_X || opnd->qualifier == AARCH64_OPND_QLF_SP%s, %s %s%s, %sopnd->qualifier == AARCH64_OPND_QLF_Xv%d.%s%s[%s]v%dv%d.d1p%dp%d/%sp%d.%spn%dpn%d/%spn%d.%sz%dz%d.%sza%d.%sza%d%c.%sw%d:%dvgx2vgx4%s%s[%s, %s%s%s%s%s]%s.za%s%s%s[%s, %s%s%s%s%s]za%d%c%s%s%s [%s, %s%s%s]sm%s[%s, %s]enum_value < ARRAY_SIZE (aarch64_sme_vlxn_array)enum_value < ARRAY_SIZE (aarch64_brbop_array)C%li#%.1fenum_value < ARRAY_SIZE (aarch64_sve_pattern_array)enum_value < ARRAY_SIZE (aarch64_sve_prfop_array)#0x%-20x#0x%-20lx#0.0#0x%lx#%.18e#0x%x%s = %sx%dreading from a write-only registerwriting to a read-only registers%u_%u_c%u_c%u_%u#0x%02xzt0{%s}%s!accdata_el1actlr_el1actlr_el2actlr_el3afsr0_el1afsr0_el12afsr0_el2afsr0_el3afsr1_el1afsr1_el12afsr1_el2afsr1_el3aidr_el1allintamair_el1amair_el12amair_el2amair_el3amair2_el1amair2_el12amair2_el2amair2_el3amcfgr_el0amcg1idr_el0amcgcr_el0amcntenclr0_el0amcntenclr1_el0amcntenset0_el0amcntenset1_el0amcr_el0amevcntr00_el0amevcntr01_el0amevcntr02_el0amevcntr03_el0amevcntr10_el0amevcntr110_el0amevcntr111_el0amevcntr112_el0amevcntr113_el0amevcntr114_el0amevcntr115_el0amevcntr11_el0amevcntr12_el0amevcntr13_el0amevcntr14_el0amevcntr15_el0amevcntr16_el0amevcntr17_el0amevcntr18_el0amevcntr19_el0amevcntvoff00_el2amevcntvoff010_el2amevcntvoff011_el2amevcntvoff012_el2amevcntvoff013_el2amevcntvoff014_el2amevcntvoff015_el2amevcntvoff01_el2amevcntvoff02_el2amevcntvoff03_el2amevcntvoff04_el2amevcntvoff05_el2amevcntvoff06_el2amevcntvoff07_el2amevcntvoff08_el2amevcntvoff09_el2amevcntvoff10_el2amevcntvoff110_el2amevcntvoff111_el2amevcntvoff112_el2amevcntvoff113_el2amevcntvoff114_el2amevcntvoff115_el2amevcntvoff11_el2amevcntvoff12_el2amevcntvoff13_el2amevcntvoff14_el2amevcntvoff15_el2amevcntvoff16_el2amevcntvoff17_el2amevcntvoff18_el2amevcntvoff19_el2amevtyper00_el0amevtyper01_el0amevtyper02_el0amevtyper03_el0amevtyper10_el0amevtyper110_el0amevtyper111_el0amevtyper112_el0amevtyper113_el0amevtyper114_el0amevtyper115_el0amevtyper11_el0amevtyper12_el0amevtyper13_el0amevtyper14_el0amevtyper15_el0amevtyper16_el0amevtyper17_el0amevtyper18_el0amevtyper19_el0amuserenr_el0apdakeyhi_el1apdakeylo_el1apdbkeyhi_el1apdbkeylo_el1apgakeyhi_el1apgakeylo_el1apiakeyhi_el1apiakeylo_el1apibkeyhi_el1apibkeylo_el1brbcr_el1brbcr_el12brbcr_el2brbfcr_el1brbidr0_el1brbinf0_el1brbinf10_el1brbinf11_el1brbinf12_el1brbinf13_el1brbinf14_el1brbinf15_el1brbinf16_el1brbinf17_el1brbinf18_el1brbinf19_el1brbinf1_el1brbinf20_el1brbinf21_el1brbinf22_el1brbinf23_el1brbinf24_el1brbinf25_el1brbinf26_el1brbinf27_el1brbinf28_el1brbinf29_el1brbinf2_el1brbinf30_el1brbinf31_el1brbinf3_el1brbinf4_el1brbinf5_el1brbinf6_el1brbinf7_el1brbinf8_el1brbinf9_el1brbinfinj_el1brbsrc0_el1brbsrc10_el1brbsrc11_el1brbsrc12_el1brbsrc13_el1brbsrc14_el1brbsrc15_el1brbsrc16_el1brbsrc17_el1brbsrc18_el1brbsrc19_el1brbsrc1_el1brbsrc20_el1brbsrc21_el1brbsrc22_el1brbsrc23_el1brbsrc24_el1brbsrc25_el1brbsrc26_el1brbsrc27_el1brbsrc28_el1brbsrc29_el1brbsrc2_el1brbsrc30_el1brbsrc31_el1brbsrc3_el1brbsrc4_el1brbsrc5_el1brbsrc6_el1brbsrc7_el1brbsrc8_el1brbsrc9_el1brbsrcinj_el1brbtgt0_el1brbtgt10_el1brbtgt11_el1brbtgt12_el1brbtgt13_el1brbtgt14_el1brbtgt15_el1brbtgt16_el1brbtgt17_el1brbtgt18_el1brbtgt19_el1brbtgt1_el1brbtgt20_el1brbtgt21_el1brbtgt22_el1brbtgt23_el1brbtgt24_el1brbtgt25_el1brbtgt26_el1brbtgt27_el1brbtgt28_el1brbtgt29_el1brbtgt2_el1brbtgt30_el1brbtgt31_el1brbtgt3_el1brbtgt4_el1brbtgt5_el1brbtgt6_el1brbtgt7_el1brbtgt8_el1brbtgt9_el1brbtgtinj_el1brbts_el1ccsidr2_el1ccsidr_el1clidr_el1cntfrq_el0cnthctl_el2cnthp_ctl_el2cnthp_cval_el2cnthp_tval_el2cnthps_ctl_el2cnthps_cval_el2cnthps_tval_el2cnthv_ctl_el2cnthv_cval_el2cnthv_tval_el2cnthvs_ctl_el2cnthvs_cval_el2cnthvs_tval_el2cntkctl_el1cntkctl_el12cntp_ctl_el0cntp_ctl_el02cntp_cval_el0cntp_cval_el02cntp_tval_el0cntp_tval_el02cntpct_el0cntpctss_el0cntpoff_el2cntps_ctl_el1cntps_cval_el1cntps_tval_el1cntv_ctl_el0cntv_ctl_el02cntv_cval_el0cntv_cval_el02cntv_tval_el0cntv_tval_el02cntvct_el0cntvctss_el0cntvoff_el2contextidr_el1contextidr_el12contextidr_el2cpacr_el1cpacr_el12cptr_el2cptr_el3csrcr_el0csrcr_el1csrcr_el12csrcr_el2csridr_el0csrptr_el0csrptr_el1csrptr_el12csrptr_el2csrptridx_el0csrptridx_el1csrptridx_el2csselr_el1ctr_el0currenteldacr32_el2daifdbgauthstatus_el1dbgbcr0_el1dbgbcr10_el1dbgbcr11_el1dbgbcr12_el1dbgbcr13_el1dbgbcr14_el1dbgbcr15_el1dbgbcr1_el1dbgbcr2_el1dbgbcr3_el1dbgbcr4_el1dbgbcr5_el1dbgbcr6_el1dbgbcr7_el1dbgbcr8_el1dbgbcr9_el1dbgbvr0_el1dbgbvr10_el1dbgbvr11_el1dbgbvr12_el1dbgbvr13_el1dbgbvr14_el1dbgbvr15_el1dbgbvr1_el1dbgbvr2_el1dbgbvr3_el1dbgbvr4_el1dbgbvr5_el1dbgbvr6_el1dbgbvr7_el1dbgbvr8_el1dbgbvr9_el1dbgclaimclr_el1dbgclaimset_el1dbgdtr_el0dbgdtrrx_el0dbgdtrtx_el0dbgprcr_el1dbgvcr32_el2dbgwcr0_el1dbgwcr10_el1dbgwcr11_el1dbgwcr12_el1dbgwcr13_el1dbgwcr14_el1dbgwcr15_el1dbgwcr1_el1dbgwcr2_el1dbgwcr3_el1dbgwcr4_el1dbgwcr5_el1dbgwcr6_el1dbgwcr7_el1dbgwcr8_el1dbgwcr9_el1dbgwvr0_el1dbgwvr10_el1dbgwvr11_el1dbgwvr12_el1dbgwvr13_el1dbgwvr14_el1dbgwvr15_el1dbgwvr1_el1dbgwvr2_el1dbgwvr3_el1dbgwvr4_el1dbgwvr5_el1dbgwvr6_el1dbgwvr7_el1dbgwvr8_el1dbgwvr9_el1dczid_el0disr_el1ditdlr_el0dspsr_el0elr_el1elr_el12elr_el2elr_el3erridr_el1errselr_el1erxaddr_el1erxctlr_el1erxfr_el1erxgsr_el1erxmisc0_el1erxmisc1_el1erxmisc2_el1erxmisc3_el1erxpfgcdn_el1erxpfgctl_el1erxpfgf_el1erxstatus_el1esr_el1esr_el12esr_el2esr_el3far_el1far_el12far_el2far_el3fpcrfpexc32_el2fpmrfpsrgcspr_el0gcspr_el1gcspr_el2gcspr_el12gcspr_el3gcscre0_el1gcscr_el1gcscr_el2gcscr_el12gcscr_el3gcr_el1gmid_el1gpccr_el3gptbr_el3hacr_el2hafgrtr_el2hcr_el2hcrx_el2hdfgrtr_el2hdfgrtr2_el2hdfgwtr_el2hdfgwtr2_el2hfgitr_el2hfgrtr_el2hfgrtr2_el2hfgwtr_el2hfgw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tdddd9tttt8ddddopcodeinst->opcode->operands[2] == AARCH64_OPND_Emvaluethe three register operands must be distinct from one anotherdestination register differs from preceding instructionsource register differs from preceding instructionsize register differs from preceding instructioninstinsn_sequenceinstruction opens new dependency sequence without ending previous oneprevious `movprfx' sequence not closedSVE instruction expected after `movprfx'SVE `movprfx' compatible instruction expectedblk_dest.type == AARCH64_OPND_SVE_Zdmax_elem_size != 0predicated instruction expected after `movprfx'merging predicate expected due to preceding `movprfx'predicate register differs from that in preceding `movprfx'output register of preceding `movprfx' not used in current instructionoutput register of preceding `movprfx' expected as outputoutput register of preceding `movprfx' used as inputregister size not compatible with previous `movprfx'@ @ @ @@@ @@ @@ "@@  @ @@@@@@@@ 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?Tm1Ii8Qgaarch64-dis-2.c$xaarch64_opcode_lookup_1$d__PRETTY_FUNCTION__.0aarch64_opcode_lookupaarch64_opcode_tableaarch64_find_next_opcodeaarch64_find_alias_opcodeaarch64_find_next_alias_opcodeaarch64_extract_operandaarch64_operandsaarch64_ext_regnoaarch64_ext_noneaarch64_ext_regrt_sysinsaarch64_ext_regno_pairaarch64_ext_reg_extendedaarch64_ext_reg_shiftedaarch64_ext_reg_lsl_shiftedaarch64_ext_ftaarch64_ext_reglaneaarch64_ext_simple_indexaarch64_ext_reglistaarch64_ext_ldst_reglistaarch64_ext_ldst_reglist_raarch64_ext_lut_reglistaarch64_ext_ldst_elemlistaarch64_ext_immaarch64_ext_advsimd_imm_shiftaarch64_ext_advsimd_imm_modifiedaarch64_ext_shll_immaarch64_ext_fpimmaarch64_ext_limmaarch64_ext_aimmaarch64_ext_imm_halfaarch64_ext_fbitsaarch64_ext_imm_rotate2aarch64_ext_imm_rotate1aarch64_ext_condaarch64_ext_addr_simpleaarch64_ext_addr_regoffaarch64_ext_addr_simmaarch64_ext_addr_simm10aarch64_ext_addr_uimm12aarch64_ext_addr_offsetaarch64_ext_simd_addr_postaarch64_ext_sysregaarch64_ext_pstatefieldaarch64_ext_sysins_opaarch64_ext_barrieraarch64_ext_barrier_dsb_nxsaarch64_ext_prfopaarch64_ext_hintaarch64_ext_sve_addr_ri_s4aarch64_ext_sve_addr_ri_s4xvlaarch64_ext_sve_addr_ri_s6xvlaarch64_ext_sve_addr_ri_s9xvlaarch64_ext_sve_addr_ri_u6aarch64_ext_sve_addr_rr_lslaarch64_ext_sve_addr_rz_xtwaarch64_ext_sve_addr_zi_u5aarch64_ext_sve_addr_zz_lslaarch64_ext_sve_addr_zz_sxtwaarch64_ext_sve_addr_zz_uxtwaarch64_ext_sve_aimmaarch64_ext_sve_asimmaarch64_ext_sve_float_half_oneaarch64_ext_sve_float_half_twoaarch64_ext_sve_float_zero_oneaarch64_ext_inv_limmaarch64_ext_sve_limm_movaarch64_ext_sve_scaleaarch64_ext_sve_shlimmaarch64_ext_sve_shrimmaarch64_ext_sme_za_vrs1aarch64_ext_sme_za_vrs2aarch64_ext_sme_za_tile_to_vecaarch64_ext_sve_quad_indexaarch64_ext_sve_indexaarch64_ext_sve_reglistaarch64_ext_sve_aligned_reglistaarch64_ext_sve_strided_reglistaarch64_ext_sme_za_hv_tilesaarch64_ext_sme_za_hv_tiles_rangeaarch64_ext_sme_za_arrayaarch64_ext_sme_addr_ri_u4xvlaarch64_ext_sme_sm_zaaarch64_ext_sme_pred_reg_with_indexaarch64_ext_plain_shrimmaarch64_ext_x0_to_x30aarch64_ext_rcpc3_addr_opt_offsetaarch64_ext_rcpc3_addr_offset__assert_fail(,HLMMMM\```|``zzzzЇ0PpЈ0 P!p"#$Љ%&'0(P)p*+,Њ-./00P1p234Ћ56708P9p:;<Ќ=>?0@PApBCDЍEFG0HPIpJKLЎMNO0PPQpRSTЏUVW0XPYpZ[\А]^_0`Papbcdȑ̑Бxԑxؑe8X<tMp`z.symtab.strtab.shstrtab.rela.text.data.bss.rodata.comment.note.GNU-stack.rela.eh_frame @@ &$,$1(90#BWR@   @0aaarch64-opc-2.o/0 0 0 644 45776 ` ELFP@@ C@xa*~{ C_Rdan integer registerRnRmRtRt2X16Rt_LS64Rt_SPan integer or stack pointer registerRsRaRt_SYSRd_SPRn_SPRm_SPPAIRREGthe second reg of a pairPAIRREG_OR_XZRRm_EXTan integer register with optional extensionRm_SFTan integer register with optional shiftRm_LSLan integer register with optional LSL shiftFda floating-point registerFnFmFaFtFt2Sda SIMD scalar registerSnSmVaa SIMD vector registerVdVnVmVdD1the top half of a 128-bit FP/SIMD registerVnD1Eda SIMD vector elementEnEmEm16a SIMD vector element limited to V0-V15Em8a SIMD vector element limited to V0-V7Em_INDEX1_14a SIMD vector without a type qualifier encoding a bit indexEm_INDEX2_13Em_INDEX3_12LVna SIMD vector register listLVtLVt_ALLVn_LUTLEta SIMD vector element listCRna 4-bit opcode field named for historical reasons C0 - C15CRmIDXan immediate as the index of the least significant byteMASKIMM_VLSLa left shift amount for an AdvSIMD registerIMM_VLSRa right shift amount for an AdvSIMD registerSIMD_IMMan immediateSIMD_IMM_SFTan 8-bit unsigned immediate with optional shiftSIMD_FPIMMan 8-bit floating-point constantSHLL_IMMan immediate shift amount of 8, 16 or 32IMM00FPIMM00.0FPIMMIMMRthe right rotate amountIMMSthe leftmost bit number to be moved from the sourceWIDTHthe width of the bit-fieldIMMIMM_2UIMM3_OP1a 3-bit unsigned immediateUIMM3_OP2UIMM4a 4-bit unsigned immediateUIMM4_ADDGa 4-bit unsigned Logical Address Tag modifierUIMM7a 7-bit unsigned immediateUIMM10a 10-bit unsigned multiple of 16BIT_NUMthe bit number to be testedEXCEPTIONa 16-bit unsigned immediateUNDEFINEDCCMP_IMMa 5-bit unsigned immediateSIMM5a 5-bit signed immediateNZCVa flag bit specifier giving an alternative value for each flagLIMMLogical immediateAIMMa 12-bit unsigned immediate with optional left shift of 12 bitsHALFa 16-bit immediate with optional left shiftFBITSthe number of bits after the binary point in the fixed-point valueIMM_MOVIMM_ROT1a 2-bit rotation specifier for complex arithmetic operationsIMM_ROT2IMM_ROT3a 1-bit rotation specifier for complex arithmetic operationsCONDa conditionCOND1one of the standard conditions, excluding AL and NV.ADDR_ADRP21-bit PC-relative address of a 4KB pageADDR_PCREL1414-bit PC-relative addressADDR_PCREL1919-bit PC-relative addressADDR_PCREL2121-bit PC-relative addressADDR_PCREL2626-bit PC-relative addressADDR_SIMPLEan address with base register (no offset)ADDR_REGOFFan address with register offsetADDR_SIMM7an address with 7-bit signed immediate offsetADDR_SIMM9an address with 9-bit signed immediate offsetADDR_SIMM9_2an address with 9-bit negative or unaligned immediate offsetADDR_SIMM10an address with an optional 10-bit scaled, signed immediate offsetADDR_SIMM11an address with 11-bit signed immediate (multiple of 16) offsetADDR_UIMM12an address with scaled, unsigned immediate offsetADDR_SIMM13an address with 13-bit signed immediate (multiple of 16) offsetSIMD_ADDR_SIMPLEADDR_OFFSETan address with an optional 8-bit signed immediate offsetSIMD_ADDR_POSTa post-indexed address with immediate or register incrementSYSREGa system registerSYSREG128a 128-bit system registerPSTATEFIELDa PSTATE field nameSYSREG_ATan address translation operation specifierSYSREG_DCa data cache maintenance operation specifierSYSREG_ICan instruction cache maintenance operation specifierSYSREG_TLBIa TBL invalidation operation specifierSYSREG_TLBIPa 128-bit TBL invalidation operation specifierSYSREG_SRa Speculation Restriction option name (RCTX)BARRIERa barrier option nameBARRIER_DSB_NXSthe DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediateBARRIER_ISBthe ISB option name SY or an optional 4-bit unsigned immediatePRFOPa prefetch operation specifierRPRFMOPa range prefetch operation specifierBARRIER_PSBthe PSB/TSB option name CSYNCBARRIER_GCSBthe GCSB option name DSYNCBTI_TARGETBTI targets j/c/jcBRBOPBranch Record Buffer operation operandRt_IN_SYS_ALIASESRt register with defaults for SYS aliasesLSE128_RtLSE128_Rt2SVE_ADDR_RI_S4x16an address with a 4-bit signed offset, multiplied by 16SVE_ADDR_RI_S4x32an address with a 4-bit signed offset, multiplied by 32SVE_ADDR_RI_S4xVLan address with a 4-bit signed offset, multiplied by VLSVE_ADDR_RI_S4x2xVLan address with a 4-bit signed offset, multiplied by 2*VLSVE_ADDR_RI_S4x3xVLan address with a 4-bit signed offset, multiplied by 3*VLSVE_ADDR_RI_S4x4xVLan address with a 4-bit signed offset, multiplied by 4*VLSVE_ADDR_RI_S6xVLan address with a 6-bit signed offset, multiplied by VLSVE_ADDR_RI_S9xVLan address with a 9-bit signed offset, multiplied by VLSVE_ADDR_RI_U6an address with a 6-bit unsigned offsetSVE_ADDR_RI_U6x2an address with a 6-bit unsigned offset, multiplied by 2SVE_ADDR_RI_U6x4an address with a 6-bit unsigned offset, multiplied by 4SVE_ADDR_RI_U6x8an address with a 6-bit unsigned offset, multiplied by 8SVE_ADDR_Ran address with an optional scalar register offsetSVE_ADDR_RRan address with a scalar register offsetSVE_ADDR_RR_LSL1SVE_ADDR_RR_LSL2SVE_ADDR_RR_LSL3SVE_ADDR_RR_LSL4SVE_ADDR_RXSVE_ADDR_RX_LSL1SVE_ADDR_RX_LSL2SVE_ADDR_RX_LSL3SVE_ADDR_RX_LSL4SVE_ADDR_ZXvector of address with a scalar register offsetSVE_ADDR_RZan address with a vector register offsetSVE_ADDR_RZ_LSL1SVE_ADDR_RZ_LSL2SVE_ADDR_RZ_LSL3SVE_ADDR_RZ_XTW_14SVE_ADDR_RZ_XTW_22SVE_ADDR_RZ_XTW1_14SVE_ADDR_RZ_XTW1_22SVE_ADDR_RZ_XTW2_14SVE_ADDR_RZ_XTW2_22SVE_ADDR_RZ_XTW3_14SVE_ADDR_RZ_XTW3_22SVE_ADDR_ZI_U5an address with a 5-bit unsigned offsetSVE_ADDR_ZI_U5x2an address with a 5-bit unsigned offset, multiplied by 2SVE_ADDR_ZI_U5x4an address with a 5-bit unsigned offset, multiplied by 4SVE_ADDR_ZI_U5x8an address with a 5-bit unsigned offset, multiplied by 8SVE_ADDR_ZZ_LSLSVE_ADDR_ZZ_SXTWSVE_ADDR_ZZ_UXTWSVE_AIMMa 9-bit unsigned arithmetic operandSVE_ASIMMa 9-bit signed arithmetic operandSVE_FPIMM8an 8-bit floating-point immediateSVE_I1_HALF_ONEeither 0.5 or 1.0SVE_I1_HALF_TWOeither 0.5 or 2.0SVE_I1_ZERO_ONEeither 0.0 or 1.0SVE_IMM_ROT1SVE_IMM_ROT2SVE_IMM_ROT3SVE_INV_LIMMan inverted 13-bit logical immediateSVE_LIMMa 13-bit logical immediateSVE_LIMM_MOVa 13-bit logical move immediateSVE_PATTERNan enumeration value such as POW2SVE_PATTERN_SCALEDSVE_PRFOPan enumeration value such as PLDL1KEEPSVE_Pdan SVE predicate registerSVE_PNdan SVE predicate-as-counter registerSVE_Pg3SVE_Pg4_5SVE_Pg4_10SVE_PNg4_10SVE_Pg4_16SVE_PmSVE_PnSVE_PNnSVE_PtSVE_PNtSVE_Rman integer register or zeroSVE_Rn_SPan integer register or SPSVE_SHLIMM_PREDa shift-left immediate operandSVE_SHLIMM_UNPREDSVE_SHLIMM_UNPRED_22SVE_SHRIMM_PREDa shift-right immediate operandSVE_SHRIMM_UNPREDSVE_SHRIMM_UNPRED_22SVE_SIMM5SVE_SIMM5BSVE_SIMM6a 6-bit signed immediateSVE_SIMM8an 8-bit signed immediateSVE_UIMM3SVE_UIMM7SVE_UIMM8an 8-bit unsigned immediateSVE_UIMM8_53SVE_UIMM4SVE_VZna SIMD registerSVE_VdSVE_VmSVE_VnSME_ZA_array_vrsb_1ZA0 tileSME_ZA_array_vrsh_11 bit ZA tileSME_ZA_array_vrss_12 ZA tileSME_ZA_array_vrsd_13 ZA tileSME_ZA_array_vrsb_2SME_ZA_array_vrsh_2SME_ZA_array_vrss_22 bit ZA tileSME_ZA_array_vrsd_23 bit ZA tileSME_ZA_ARRAY4ZA tile to vector registerSVE_Za_5an SVE vector registerSVE_Za_16SVE_ZdSVE_Zm_5SVE_Zm_16SVE_Zm1_23_INDEXan indexed SVE vector registerSVE_Zm2_22_INDEXSVE_Zm3_INDEXSVE_Zm3_11_INDEXSVE_Zm3_12_INDEXSVE_Zm3_19_INDEXSVE_Zm3_22_INDEXSVE_Zm3_10_INDEXSVE_Zm4_11_INDEXSVE_Zm4_INDEXSVE_ZnSVE_Zn_INDEXSVE_Zn_5_INDEXa 5 bit indexed SVE vector registerSVE_ZnxNa list of SVE vector registersSVE_ZtSVE_ZtxNSME_Zdnx2SME_Zdnx4SME_Zdnx4_STRIDEDSME_ZmSME_Zmx2SME_Zmx4SME_Znx2SME_Znx2_BIT_INDEXSME_Znx4SME_Ztx2_STRIDEDSME_Ztx4_STRIDEDSME_ZAda_1ban SME ZA tile ZA0-ZA1SME_ZAda_2ban SME ZA tile ZA0-ZA3SME_ZAda_3ban SME ZA tile ZA0-ZA7SME_ZA_HV_idx_srcan SME horizontal or vertical vector access registerSME_ZA_HV_idx_srcxNSME_ZA_HV_idx_destSME_ZA_HV_idx_destxNSME_Pdx2a list of SVE predicate registersSME_PdxNSME_PmSME_PNd3SME_PNg3SME_PNnSME_PNn3_INDEX1an indexed SVE predicate-as-counter registerSME_PNn3_INDEX2SME_list_of_64bit_tilesa list of 64-bit ZA element tilesSME_ZA_HV_idx_ldstrSME_ZA_array_off1x4ZA arraySME_ZA_array_off2x2SME_ZA_array_off2x4SME_ZA_array_off3_0SME_ZA_array_off3_5SME_ZA_array_off3x2SME_ZA_array_off4SME_ADDR_RI_U4xVLmemory offsetSME_SM_ZAstreaming modeSME_PnT_Wm_immSource scalable predicate register with index SME_SHRIMM4SME_SHRIMM5SME_Zm_INDEX1SME_Zm_INDEX2SME_Zm_INDEX2_3SME_Zm_INDEX3_1SME_Zm_INDEX3_2SME_Zm_INDEX3_3SME_Zm_INDEX3_10SME_Zm_INDEX4_1SME_Zm_INDEX4_2SME_Zm_INDEX4_3SME_Zm_INDEX4_10SME_Zn_INDEX1_16SME_Zn_INDEX2_15SME_Zn_INDEX2_16SME_Zn_INDEX3_14SME_Zn_INDEX3_15SME_Zn_INDEX4_14SVE_Zn0_INDEXan SVE vector register with option zero indexSVE_Zn1_17_INDEXan SVE vector register with optional one bit indexSVE_Zn2_18_INDEXan SVE vector register with optional two bit indexSVE_Zn3_22_INDEXan SVE vector register with optional three bit indexSVE_Zd0_INDEXSVE_Zd1_17_INDEXSVE_Zd2_18_INDEXSVE_Zd3_22_INDEXSME_VLxN_10VLx2 or VLx4SME_VLxN_13SME_ZT0ZT0SME_ZT0_INDEXa ZT0 indexSME_ZT0_INDEX2_12SME_ZT0_LIST{ ZT0 }TME_UIMM16a 16-bit unsigned immediate for TME tcancelSM3_IMM2an indexed SM3 vector immediateMOPS_ADDR_Rda register destination address with writebackMOPS_ADDR_Rsa register source address with writebackMOPS_WB_Rdan integer register with writebackCSSC_SIMM8CSSC_UIMM8RCPC3_ADDR_OPT_POSTINDan address with post-incrementing by ammount of loaded bytesRCPC3_ADDR_OPT_PREIND_WBan address with pre-incrementing with write-back by ammount of stored bytesRCPC3_ADDR_POSTINDRCPC3_ADDR_PREIND_WBRCPC3_ADDR_OFFSETDUMMY                                 ts                       p          # C c    # C c   # C c   # C c  K J #J CJ cJ Jn Jo #Jn #Jo CJn CJo cJn cJo K #K CK cK KJ KJ KJ ^ ^ ] M M M d e f 8_` 8_` 8_` b b c 9 9 : ; < < = > ? ? @ @AB kY k hmW #kY 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%1-3,5Qvmla%v.i%20-21s %13-15,22Q, %17-19,7Q, %0-3rvmlaldav%5Ax%v.%u%16s %13-15l, %20-22h, %17-19,7Q, %1-3Qvmlalv%5A%v.%u%16s %13-15l, %20-22h, %17-19,7Q, %1-3Qvmlav%5A%v.%u%16s %13-15l, %17-19,7Q, %1-3Qvmlav%5A%v.%u8 %13-15l, %17-19,7Q, %1-3Qvmladav%5Ax%v.%u%16s %13-15l, %17-19,7Q, %1-3Qvmladav%5Ax%v.%u8 %13-15l, %17-19,7Q, %1-3Qvmlas%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvrmlsldavh%5A%X%v.s32 %13-15l, %20-22h, %17-19,7Q, %1-3Qvmlsldav%5A%X%v.%u%16s %13-15l, %20-22h, %17-19,7Q, %1-3Qvmlsdav%5A%X%v.s%16s %13-15l, %17-19,7Q, %1-3Qvmlsdav%5A%X%v.s8 %13-15l, %17-19,7Q, %1-3Qvmov.f16 %7,16-19F, %12-15rvmov.f16 %12-15r, %7,16-19Fvmov%c.%5-6,21-22s %{R:%17-19,7Q[%N]%}, %12-15rvorr%v.i%8-11s %13-15,22Q, %Evqshl%v.%u%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vqshlu%v.s%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vrshr%v.%u%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vshl%v.i%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vshr%v.%u%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vsli%v.%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vsri%v.%19-21s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%} @ instruction: %0-31xvmov%v.%5,8-11s %13-15,22Q, %Evmov%c %0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}vmov%c %0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}vmov%c %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19rvmov%c %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19rvmov%c.%u%5-6,21-22s %12-15r, %{R:%17-19,7Q[%N]%}vshll%T%v.%u%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vmovl%T%v.%u%19-20s %13-15,22Q, %1-3,5Qvmovn%T%v.i%18-19s %13-15,22Q, %1-3,5Qvmovx.f16 %22,12-15F, %5,0-3Fvmul%v.f%20s %13-15,22Q, %17-19,7Q, %1-3,5Qvmul%v.f%28s %13-15,22Q, %17-19,7Q, %0-3rvmul%v.i%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvmul%v.i%20-21s %13-15,22Q, %17-19,7Q, %0-3rvmulh%v.%u%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvrmulh%v.%u%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvmull%T%v.%u%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvmull%T%v.%28s %13-15,22Q, %17-19,7Q, %1-3,5Qvmvn%v.i%8-11s %13-15,22Q, %Evmvn%v %13-15,22Q, %1-3,5Qvneg%v.f%18-19s %13-15,22Q, %1-3,5Qvneg%v.s%18-19s %13-15,22Q, %1-3,5Qvorn%v %13-15,22Q, %17-19,7Q, %1-3,5Qvorr%v %13-15,22Q, %17-19,7Q, %1-3,5Qvmov%v %13-15,22Q, %17-19,7Qvqdmull%T%v.s%28s %13-15,22Q, %17-19,7Q, %1-3,5Qvpnot%vvpsel%v %13-15,22Q, %17-19,7Q, %1-3,5Qvqabs%v.s%18-19s %13-15,22Q, %17-19,7Q, %1-3,5Qvqadd%v.%u%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqadd%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqdmull%T%v.s%28s %13-15,22Q, %17-19,7Q, %0-3rvqmovn%T%v.%u%18-19s %13-15,22Q, %1-3,5Qvqmovun%T%v.s%18-19s %13-15,22Q, %1-3,5Qvqdmladh%X%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqrdmladh%X%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqdmlah%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqrdmlah%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqdmlash%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqrdmlash%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqdmlsdh%X%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqrdmlsdh%X%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqdmulh%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqrdmulh%v.s%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqdmulh%v.s%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqrdmulh%v.s%20-21s %13-15,22Q, %17-19,7Q, %0-3rvqneg%v.s%18-19s %13-15,22Q, %1-3,5Qvqrshl%v.%u%20-21s %13-15,22Q, %1-3,5Q, %17-19,7Qvqrshl%v.%u%18-19s %13-15,22Q, %0-3rvqrshrn%T%v.%u%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vqrshrun%T%v.s%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vqshl%v.%u%18-19s %13-15,22Q, %0-3rvqshl%v.%u%20-21s %13-15,22Q, %1-3,5Q, %17-19,7Qvqshrn%T%v.%u%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vqshrun%T%v.s%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vqsub%v.%u%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvqsub%v.%u%20-21s %13-15,22Q, %17-19,7Q, %0-3rvrev16%v.8 %13-15,22Q, %1-3,5Qvrev32%v.%18-19s %13-15,22Q, %1-3,5Qvrev64%v.%18-19s %13-15,22Q, %1-3,5Qvrint%m%v.f%18-19s %13-15,22Q, %1-3,5Qvrmlalvh%5A%v.%u32 %13-15l, %20-22h, %17-19,7Q, %1-3Qvrmlaldavh%5Ax%v.%u32 %13-15l, %20-22h, %17-19,7Q, %1-3Qvrshl%v.%u%20-21s %13-15,22Q, %1-3,5Q, %17-19,7Qvrshl%v.%u%18-19s %13-15,22Q, %0-3rvrshrn%T%v.i%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vsbc%12I%v.i32 %13-15,22Q, %17-19,7Q, %1-3,5Qvshl%v.%u%18-19s %13-15,22Q, %0-3rvshl%v.%u%20-21s %13-15,22Q, %1-3,5Q, %17-19,7Qvshlc%v %13-15,22Q, %0-3r, %{I:#%16-20d%}vshll%T%v.%u%18-19s %13-15,22Q, %1-3,5Q, %{I:#%18-19d%}vshrn%T%v.i%19-20s %13-15,22Q, %1-3,5Q, %{I:#%16-18d%}vst2%5d.%7-8s %B, [%16-19r]vst2%5d.%7-8s %B, [%16-19r]!vst4%5-6d.%7-8s %B, [%16-19r]vst4%5-6d.%7-8s %B, [%16-19r]!vstrb%v.%7-8s %13-15,22Q, [%16-19r, %1-3,5Q]vstrh%v.%7-8s %13-15,22Q, [%16-19r, %1-3,5Q%o]vstrw%v.%7-8s %13-15,22Q, [%16-19r, %1-3,5Q%o]vstrd%v.64 %13-15,22Q, [%16-19r, %1-3,5Q%o]vstrw%v.32 %13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%wvstrd%v.64 %13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%wvstrb%v.%7-8s %13-15Q, %dvstrh%v.%7-8s %13-15Q, %dvstrb%v.8 %13-15,22Q, %dvstrh%v.16 %13-15,22Q, %dvstrw%v.32 %13-15,22Q, %dvsub%v.f%20s %13-15,22Q, %17-19,7Q, %1-3,5Qvsub%v.f%28s %13-15,22Q, %17-19,7Q, %0-3rvsub%v.i%20-21s %13-15,22Q, %17-19,7Q, %1-3,5Qvsub%v.i%20-21s %13-15,22Q, %17-19,7Q, %0-3rasrl%c %17-19l, %9-11h, %jasrl%c %17-19l, %9-11h, %12-15Slsll%c %17-19l, %9-11h, %jlsll%c %17-19l, %9-11h, %12-15Slsrl%c %17-19l, %9-11h, %jsqrshrl%c %17-19l, %9-11h, %k, %12-15Ssqrshr%c %16-19S, %12-15Ssqshll%c %17-19l, %9-11h, %jsqshl%c %16-19S, %jsrshrl%c %17-19l, %9-11h, %jsrshr%c %16-19S, %juqrshll%c %17-19l, %9-11h, %k, %12-15Suqrshl%c %16-19S, %12-15Suqshll%c %17-19l, %9-11h, %juqshl%c %16-19S, %jurshrl%c %17-19l, %9-11h, %jurshr%c %16-19S, %jcsinc %8-11S, %16-19Z, %0-3Z, %4-7ccsinv %8-11S, %16-19Z, %0-3Z, %4-7ccset %8-11S, %4-7Ccsetm %8-11S, %4-7Ccsel %8-11S, %16-19Z, %0-3Z, %4-7ccsneg %8-11S, %16-19Z, %0-3Z, %4-7ccinc %8-11S, %16-19Z, %4-7Ccinv %8-11S, %16-19Z, %4-7Ccneg %8-11S, %16-19Z, %4-7CM1 1P @1PQQP@p`p@PGppHPQQ @ Q@Q @@ @ Q @0p@Q@pWR0QPQ`p m@QnQ@ p@ Q! 1P @1P Q Q P@p`p@P _PQ @1p P Q P Q @1p@Q@p@Q@p q0P _@Q 6P  7@Q 8? 8? 9@Qin~j`poQk`pln~_*P+P,@-./ X!X"#$@Q3 PQ ?  PQ3 P Q ?  @pUQUQSQTQSQTQV@p\QZQXQYQ ;  ;  < DPwPxP~PPPPPBp=P =P??@@ A @J@K1 I@  P Q `1pP Q`pQQLQM1QBpC FP0QEP Q>P QN0QM11Q@PQ`pO`0pP3Q1]Q^Q_`p`@pa`pb@pcQdQe@ Qf@ Qg`ph`prPQs3tAuv1yPQz@{PQ`p@@ :@Q[Q[Q|@Q}`30Q`1@Q1__0P1P2@P345%X&X'() @ Q @0p@Q@p/P?-PP? PP?-Q-P?Q??P?/Q?/P? Q PQ?P?Q?P?PP__PPPPPnop @ (mov r0, r0)udf %{I:#%e%}bx%c %0-3r%Tmul%20's%c %16-19R, %0-3R, %8-11Rmla%20's%c %16-19R, %0-3R, %8-11R, %12-15Rswp%22'b%c %12-15RU, %0-3Ru, [%16-19RuU]%22?sumull%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R%22?sumlal%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11Resbdfbsevlhlt %{I:0x%16-19X%12-15X%8-11X%0-3X%}stlex%c %12-15r, %0-3r, [%16-19R]ldaex%c %12-15r, [%16-19R]stlexd%c %12-15r, %0-3r, %0-3T, [%16-19R]ldaexd%c %12-15r, %12-15T, [%16-19R]stlexb%c %12-15r, %0-3r, [%16-19R]ldaexb%c %12-15r, [%16-19R]stlexh%c %12-15r, %0-3r, [%16-19R]ldaexh%c %12-15r, [%16-19R]stl%c %0-3r, [%16-19R]lda%c %12-15r, [%16-19R]stlb%c %0-3r, [%16-19R]ldab%c %12-15r, [%16-19R]stlh%c %0-3r, [%16-19R]ldah%c %12-15r, [%16-19R]crc32b %12-15R, %16-19R, %0-3Rcrc32h %12-15R, %16-19R, %0-3Rcrc32w %12-15R, %16-19R, %0-3Rcrc32cb %12-15R, %16-19R, %0-3Rcrc32ch %12-15R, %16-19R, %0-3Rcrc32cw %12-15R, %16-19R, %0-3Rsetpan %{I:#%9-9d%}eret%chvc%c %esdiv%c %16-19r, %0-3r, %8-11rudiv%c %16-19r, %0-3r, %8-11rpldw %acsdbssbbpssbbpli %Pdbg%c %{I:#%0-3d%}dmb %Udsb %Uisb %Unop%c {%{I:%0-7d%}}bfc%c %12-15R, %Ebfi%c %12-15R, %0-3r, %Emls%c %16-19R, %0-3R, %8-11R, %12-15Rstrht%c %12-15R, %Sldr%6's%5?hbt%c %12-15R, %Smovw%c %12-15R, %Vmovt%c %12-15R, %Vrbit%c %12-15R, %0-3R%22?usbfx%c %12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}smc%c %eclrexldrexb%c %12-15R, [%16-19R]ldrexd%c %12-15r, [%16-19R]ldrexh%c %12-15R, [%16-19R]strexb%c %12-15R, %0-3R, [%16-19R]strexd%c %12-15R, %0-3r, [%16-19R]strexh%c %12-15R, %0-3R, [%16-19R]sbyield%cwfe%cwfi%csev%ccpsie %{B:%8'a%7'i%6'f%}cpsie %{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}cpsid %{B:%8'a%7'i%6'f%}cpsid %{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}cps %{I:#%0-4d%}pkhbt%c %12-15R, %16-19R, %0-3Rpkhbt%c %12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}pkhtb%c %12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}pkhtb%c %12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}ldrex%c %{R:r%12-15d%}, [%16-19R]qadd16%c %12-15R, %16-19R, %0-3Rqadd8%c %12-15R, %16-19R, %0-3Rqasx%c %12-15R, %16-19R, %0-3Rqsub16%c %12-15R, %16-19R, %0-3Rqsub8%c %12-15R, %16-19R, %0-3Rqsax%c %12-15R, %16-19R, %0-3Rsadd16%c %12-15R, %16-19R, %0-3Rsadd8%c %12-15R, %16-19R, %0-3Rsasx%c %12-15R, %16-19R, %0-3Rshadd16%c %12-15R, %16-19R, %0-3Rshadd8%c %12-15R, %16-19R, %0-3Rshasx%c %12-15R, %16-19R, %0-3Rshsub16%c %12-15R, %16-19R, %0-3Rshsub8%c %12-15R, %16-19R, %0-3Rshsax%c %12-15R, %16-19R, %0-3Rssub16%c %12-15R, %16-19R, %0-3Rssub8%c %12-15R, %16-19R, %0-3Rssax%c %12-15R, %16-19R, %0-3Ruadd16%c %12-15R, %16-19R, %0-3Ruadd8%c %12-15R, %16-19R, %0-3Ruasx%c %12-15R, %16-19R, %0-3Ruhadd16%c %12-15R, %16-19R, %0-3Ruhadd8%c %12-15R, %16-19R, %0-3Ruhasx%c %12-15R, %16-19R, %0-3Ruhsub16%c %12-15R, %16-19R, %0-3Ruhsub8%c %12-15R, %16-19R, %0-3Ruhsax%c %12-15R, %16-19R, %0-3Ruqadd16%c %12-15R, %16-19R, %0-3Ruqadd8%c %12-15R, %16-19R, %0-3Ruqasx%c %12-15R, %16-19R, %0-3Ruqsub16%c %12-15R, %16-19R, %0-3Ruqsub8%c %12-15R, %16-19R, %0-3Ruqsax%c %12-15R, %16-19R, %0-3Rusub16%c %12-15R, %16-19R, %0-3Rusub8%c %12-15R, %16-19R, %0-3Rusax%c %12-15R, %16-19R, %0-3Rrev%c %12-15R, %0-3Rrev16%c %12-15R, %0-3Rrevsh%c %12-15R, %0-3Rrfe%23?id%24?ba %16-19r%21'!sxth%c %12-15R, %0-3Rsxth%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}sxth%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}sxth%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}sxtb16%c %12-15R, %0-3Rsxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}sxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}sxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}sxtb%c %12-15R, %0-3Rsxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}sxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}sxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}uxth%c %12-15R, %0-3Ruxth%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}uxth%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}uxth%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}uxtb16%c %12-15R, %0-3Ruxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}uxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}uxtb16%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}uxtb%c %12-15R, %0-3Ruxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#8%}uxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#16%}uxtb%c %12-15R, %0-3R, %{B:ror%} %{I:#24%}sxtah%c %12-15R, %16-19r, %0-3Rsxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}sxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}sxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}sxtab16%c %12-15R, %16-19r, %0-3Rsxtab16%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}sxtab16%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}sxtab16%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}sxtab%c %12-15R, %16-19r, %0-3Rsxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}sxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}sxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}uxtah%c %12-15R, %16-19r, %0-3Ruxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}uxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}uxtah%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}uxtab16%c %12-15R, %16-19r, %0-3Ruxtab16%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}uxtab16%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}uxtab16%c %12-15R, %16-19r, %0-3R, ROR %{I:#24%}uxtab%c %12-15R, %16-19r, %0-3Ruxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}uxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}uxtab%c %12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}sel%c %12-15R, %16-19R, %0-3Rsetend %{B:%9?ble%}smuad%5'x%c %16-19R, %0-3R, %8-11Rsmusd%5'x%c %16-19R, %0-3R, %8-11Rsmlad%5'x%c %16-19R, %0-3R, %8-11R, %12-15Rsmlald%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmlsd%5'x%c %16-19R, %0-3R, %8-11R, %12-15Rsmlsld%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmmul%5'r%c %16-19R, %0-3R, %8-11Rsmmla%5'r%c %16-19R, %0-3R, %8-11R, %12-15Rsmmls%5'r%c %16-19R, %0-3R, %8-11R, %12-15Rsrs%23?id%24?ba %16-19r%21'!, %{I:#%0-4d%}ssat%c %12-15R, %{I:#%16-20W%}, %0-3Rssat%c %12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}ssat%c %12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}ssat16%c %12-15r, %{I:#%16-19W%}, %0-3rstrex%c %12-15R, %0-3R, [%16-19R]umaal%c %12-15R, %16-19R, %0-3R, %8-11Rusad8%c %16-19R, %0-3R, %8-11Rusada8%c %16-19R, %0-3R, %8-11R, %12-15Rusat%c %12-15R, %{I:#%16-20d%}, %0-3Rusat%c %12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}usat%c %12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}usat16%c %12-15R, %{I:#%16-19d%}, %0-3Rbxj%c %0-3Rbkpt %{I:0x%16-19X%12-15X%8-11X%0-3X%}blx %Bblx%c %0-3Rclz%c %12-15R, %0-3Rldrd%c %12-15r, %sstrd%c %12-15r, %spld %asmlabb%c %16-19R, %0-3R, %8-11R, %12-15Rsmlatb%c %16-19R, %0-3R, %8-11R, %12-15Rsmlabt%c %16-19R, %0-3R, %8-11R, %12-15Rsmlatt%c %16-19r, %0-3r, %8-11R, %12-15Rsmlawb%c %16-19R, %0-3R, %8-11R, %12-15Rsmlawt%c %16-19R, %0-3r, %8-11R, %12-15Rsmlalbb%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmlaltb%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmlalbt%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmlaltt%c %12-15Ru, %16-19Ru, %0-3R, %8-11Rsmulbb%c %16-19R, %0-3R, %8-11Rsmultb%c %16-19R, %0-3R, %8-11Rsmulbt%c %16-19R, %0-3R, %8-11Rsmultt%c %16-19R, %0-3R, %8-11Rsmulwb%c %16-19R, %0-3R, %8-11Rsmulwt%c %16-19R, %0-3R, %8-11Rqadd%c %12-15R, %0-3R, %16-19Rqdadd%c %12-15R, %0-3R, %16-19Rqsub%c %12-15R, %0-3R, %16-19Rqdsub%c %12-15R, %0-3R, %16-19Rpush%c {%12-15r} @ (str%c %12-15r, %a)strb%t%c %12-15R, %astr%t%c %12-15r, %astrb%c %12-15R, %astrh%c %12-15R, %sldr%6's%5?hb%c %12-15R, %sand%20's%c %12-15r, %16-19r, %oand%20's%c %12-15R, %16-19R, %oeor%20's%c %12-15r, %16-19r, %oeor%20's%c %12-15R, %16-19R, %osub%20's%c %12-15r, %16-19r, %osub%20's%c %12-15R, %16-19R, %orsb%20's%c %12-15r, %16-19r, %orsb%20's%c %12-15R, %16-19R, %oadd%20's%c %12-15r, %16-19r, %oadd%20's%c %12-15R, %16-19R, %oadc%20's%c %12-15r, %16-19r, %oadc%20's%c %12-15R, %16-19R, %osbc%20's%c %12-15r, %16-19r, %osbc%20's%c %12-15R, %16-19R, %orsc%20's%c %12-15r, %16-19r, %orsc%20's%c %12-15R, %16-19R, %omsr%c %C, %0-3rmsr%c %C, %omrs%c %12-15R, %Rtst%p%c %16-19r, %o%Otst%p%c %16-19R, %o%Oteq%p%c %16-19r, %o%Oteq%p%c %16-19R, %o%Ocmp%p%c %16-19r, %o%Ocmp%p%c %16-19R, %o%Ocmn%p%c %16-19r, %o%Ocmn%p%c %16-19R, %o%Oorr%20's%c %12-15r, %16-19r, %oorr%20's%c %12-15R, %16-19R, %omov%20's%c %12-15r, %omov%20's%c %12-15r, %0-3rlsl%20's%c %12-15R, %qlsr%20's%c %12-15R, %qasr%20's%c %12-15R, %qrrx%20's%c %12-15r, %0-3rror%20's%c %12-15R, %qbic%20's%c %12-15r, %16-19r, %obic%20's%c %12-15R, %16-19R, %omvn%20's%c %12-15r, %omvn%20's%c %12-15R, %opop%c {%12-15r} @ (ldr%c %12-15r, %a)ldrb%t%c %12-15R, %aldrt%c %12-15R, %aldr%c %12-15r, %astmfd%c %16-19R!, %mpush%c %mstm%c %16-19R%21'!, %m%22'^stm%23?id%24?ba%c %16-19R%21'!, %m%22'^ldmfd%c %16-19R!, %mpop%c %mldm%c %16-19R%21'!, %m%22'^ldm%23?id%24?ba%c %16-19R%21'!, %m%22'^b%24'l%c %bsvc%c %0-23xnop%c {%{I:%0-7d%}} @  /  L@ p@@   @@ @@@@ @@n`p@@@0p @DPp @Q@AP@` p` 00000@0Ppp`        p         ?  ?  pPPp  0 p  P 00000p00P0pPPP0Ppp0ppppPp``0`p``P`pPPPP0 Ppppp pppp pppp pppp pppp pppp pppp pppp pppp pppp pppp pppp P@PP@PPPM_pPp0@pPp0 /p 0/oPp  @@@@````  PP@P P`-@PP@PP@P P @P@P@PPPPPPPP   @@@```    000@@@``` `  ` @` ` `` PP 0p P - - - - -  - @- - - - - - -  - @- - -  @ @  blxns %3-6rbxns %3-6rsevl%chlt %0-5xsetpan %{I:#%3-3d%}nop%cnop%c {%4-7d}cbnz %0-2r, %b%Xcbz %0-2r, %b%Xit%I%Xcpsie %{B:%2'a%1'i%0'f%}%Xcpsid %{B:%2'a%1'i%0'f%}%Xmov%c %0-2r, %3-5rrev%c %0-2r, %3-5rrev16%c %0-2r, %3-5rrevsh%c %0-2r, %3-5rsetend %{B:%3?ble%}%Xsxth%c %0-2r, %3-5rsxtb%c %0-2r, %3-5ruxth%c %0-2r, %3-5ruxtb%c %0-2r, %3-5rbkpt %0-7xblx%c %3-6r%xnop%c @ (mov r8, r8)and%C %0-2r, %3-5reor%C %0-2r, %3-5rlsl%C %0-2r, %3-5rlsr%C %0-2r, %3-5rasr%C %0-2r, %3-5radc%C %0-2r, %3-5rsbc%C %0-2r, %3-5rror%C %0-2r, %3-5rtst%c %0-2r, %3-5rneg%C %0-2r, %3-5rcmp%c %0-2r, %3-5rcmn%c %0-2r, %3-5rorr%C %0-2r, %3-5rmul%C %0-2r, %3-5rbic%C %0-2r, %3-5rmvn%C %0-2r, %3-5radd%c %{R:sp%}, %{I:#%0-6W%}sub%c %{R:sp%}, %{I:#%0-6W%}bx%c %S%xadd%c %D, %Scmp%c %D, %Smov%c %D, %Spush%c %Npop%c %Oadd%C %0-2r, %3-5r, %6-8rsub%C %0-2r, %3-5r, %6-8radd%C %0-2r, %3-5r, %{I:#%6-8d%}sub%C %0-2r, %3-5r, %{I:#%6-8d%}strh%c %0-2r, [%3-5r, %6-8r]ldrh%c %0-2r, [%3-5r, %6-8r]ldrs%11?hb%c %0-2r, [%3-5r, %6-8r]str%10'b%c %0-2r, [%3-5r, %6-8r]ldr%10'b%c %0-2r, [%3-5r, %6-8r]mov%C %0-2r, %3-5rlsl%C %0-2r, %3-5r, %{I:#%6-10d%}lsr%C %0-2r, %3-5r, %sasr%C %0-2r, %3-5r, %smov%C %8-10r, %{I:#%0-7d%}cmp%c %8-10r, %{I:#%0-7d%}add%C %8-10r, %{I:#%0-7d%}sub%C %8-10r, %{I:#%0-7d%}ldr%c %8-10r, [%{R:pc%}, %{I:#%0-7W%}] @ (%0-7a)str%c %0-2r, [%3-5r, %{I:#%6-10W%}]ldr%c %0-2r, [%3-5r, %{I:#%6-10W%}]strb%c %0-2r, [%3-5r, %{I:#%6-10d%}]ldrb%c %0-2r, [%3-5r, %{I:#%6-10d%}]strh%c %0-2r, [%3-5r, %{I:#%6-10H%}]ldrh%c %0-2r, [%3-5r, %{I:#%6-10H%}]str%c %8-10r, [%{R:sp%}, %{I:#%0-7W%}]ldr%c %8-10r, [%{R:sp%}, %{I:#%0-7W%}]add%c %8-10r, %{R:pc%}, %{I:#%0-7W%} @ (adr %8-10r, %0-7a)add%c %8-10r, %{R:sp%}, %{I:#%0-7W%}stmia%c %8-10r!, %Mldmia%c %8-10r%W, %Msvc%c %0-7dudf%c %{I:#%0-7d%}b%8-11c.n %0-7B%Xb%c.n %0-10B%xGG@P@  0 @ `pF@P@G@F@@@@@@@@@@A@@A@A@A@B@@B@B@B@C@@C@C@C@@@G@D@E@F@@@@@@@R@Z@V@P@X@@@@@ @(@0@8@H@`@h@p@x@@@@@@@@@@@@@aut %{R:r12%}, %{R:lr%}, %{R:sp%}autg%c %12-15r, %16-19r, %0-3rbtibxaut%c %12-15r, %16-19r, %0-3rpac %{R:r12%}, %{R:lr%}, %{R:sp%}pacbti %{R:r12%}, %{R:lr%}, %{R:sp%}pacg%c %8-11r, %16-19r, %0-3rlctp%cle %Ple %{R:lr%}, %Pletp %{R:lr%}, %Pwls %{R:lr%}, %16-19S, %Qwlstp.%20-21s %{R:lr%}, %16-19S, %Qdls %{R:lr%}, %16-19Sdlstp.%20-21s %{R:lr%}, %16-19Sbf%c %G, %Wbfx%c %G, %16-19Sbfl%c %G, %Ybflx%c %G, %16-19Sbfcsel %G, %Z, %{B:%18-21c%}clrm%c %nsgtt %8-11r, %16-19rttt %8-11r, %16-19rtta %8-11r, %16-19rttat %8-11r, %16-19rsevl%c.wdcps%0-1dstlb%c %12-15r, [%16-19R]stlh%c %12-15r, [%16-19R]stl%c %12-15r, [%16-19R]stlexb%c %0-3r, %12-15r, [%16-19R]stlexh%c %0-3r, %12-15r, [%16-19R]stlex%c %0-3r, %12-15r, [%16-19R]stlexd%c %0-3r, %12-15r, %8-11r, [%16-19R]ldaexd%c %12-15r, %8-11r, [%16-19R]dfb%ccrc32b %8-11R, %16-19R, %0-3Rcrc32h %9-11R, %16-19R, %0-3Rcrc32w %8-11R, %16-19R, %0-3Rcrc32cb %8-11R, %16-19R, %0-3Rcrc32ch %8-11R, %16-19R, %0-3Rcrc32cw %8-11R, %16-19R, %0-3Rpli%c %admb%c %Udsb%c %Uisb%c %Usdiv%c %8-11r, %16-19r, %0-3rudiv%c %8-11r, %16-19r, %0-3rhvc%c %Vpldw%c %asmc%c %Knop%c.wyield%c.wwfe%c.wwfi%c.wsev%c.wnop%c.w {%{I:%0-7d%}}udf%c.w %Hclrex%ccpsie.w %{B:%7'a%6'i%5'f%}%Xcpsid.w %{B:%7'a%6'i%5'f%}%Xbxj%c %16-19r%xrfedb%c %16-19r%21'!rfeia%c %16-19r%21'!mrs%c %8-11r, %Dcps %{I:#%0-4d%}%Xtbb%c [%16-19r, %0-3r]%xtbh%c [%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%xcpsie %{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%Xcpsid %{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%Xsubs%c %{R:pc%}, %{R:lr%}, %{I:#%0-7d%}msr%c %C, %16-19rldrex%c %12-15r, [%16-19r]ldrex%4?hb%c %12-15r, [%16-19r]srsdb%c %16-19r%21'!, %{I:#%0-4d%}srsia%c %16-19r%21'!, %{I:#%0-4d%}sxth%c.w %8-11r, %0-3r%Ruxth%c.w %8-11r, %0-3r%Rsxtb16%c %8-11r, %0-3r%Ruxtb16%c %8-11r, %0-3r%Rsxtb%c.w %8-11r, %0-3r%Ruxtb%c.w %8-11r, %0-3r%Rstrex%c %8-11r, %12-15r, [%16-19r]ldrexd%c %12-15r, %8-11r, [%16-19r]sadd8%c %8-11r, %16-19r, %0-3rqadd8%c %8-11r, %16-19r, %0-3rshadd8%c %8-11r, %16-19r, %0-3ruadd8%c %8-11r, %16-19r, %0-3ruqadd8%c %8-11r, %16-19r, %0-3ruhadd8%c %8-11r, %16-19r, %0-3rqadd%c %8-11r, %0-3r, %16-19rqdadd%c %8-11r, %0-3r, %16-19rqsub%c %8-11r, %0-3r, %16-19rqdsub%c %8-11r, %0-3r, %16-19rsadd16%c %8-11r, %16-19r, %0-3rqadd16%c %8-11r, %16-19r, %0-3rshadd16%c %8-11r, %16-19r, %0-3ruadd16%c %8-11r, %16-19r, %0-3ruqadd16%c %8-11r, %16-19r, %0-3ruhadd16%c %8-11r, %16-19r, %0-3rrev%c.w %8-11r, %16-19rrev16%c.w %8-11r, %16-19rrbit%c %8-11r, %16-19rrevsh%c.w %8-11r, %16-19rsasx%c %8-11r, %16-19r, %0-3rqasx%c %8-11r, %16-19r, %0-3rshasx%c %8-11r, %16-19r, %0-3ruasx%c %8-11r, %16-19r, %0-3ruqasx%c %8-11r, %16-19r, %0-3ruhasx%c %8-11r, %16-19r, %0-3rsel%c %8-11r, %16-19r, %0-3rclz%c %8-11r, %16-19rssub8%c %8-11r, %16-19r, %0-3rqsub8%c %8-11r, %16-19r, %0-3rshsub8%c %8-11r, %16-19r, %0-3rusub8%c %8-11r, %16-19r, %0-3ruqsub8%c %8-11r, %16-19r, %0-3ruhsub8%c %8-11r, %16-19r, %0-3rssub16%c %8-11r, %16-19r, %0-3rqsub16%c %8-11r, %16-19r, %0-3rshsub16%c %8-11r, %16-19r, %0-3rusub16%c %8-11r, %16-19r, %0-3ruqsub16%c %8-11r, %16-19r, %0-3ruhsub16%c %8-11r, %16-19r, %0-3rssax%c %8-11r, %16-19r, %0-3rqsax%c %8-11r, %16-19r, %0-3rshsax%c %8-11r, %16-19r, %0-3rusax%c %8-11r, %16-19r, %0-3ruqsax%c %8-11r, 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%16-19r%susat%c %8-11r, %{I:#%0-4d%}, %16-19r%saddw%c %8-11r, %16-19r, %Imovw%c %8-11r, %Jsubw%c %8-11r, %16-19r, %Imovt%c %8-11r, %Jand%20's%c.w %8-11r, %16-19r, %Sbic%20's%c.w %8-11r, %16-19r, %Sorr%20's%c.w %8-11r, %16-19r, %Sorn%20's%c %8-11r, %16-19r, %Seor%20's%c.w %8-11r, %16-19r, %Sadd%20's%c.w %8-11r, %16-19r, %Sadc%20's%c.w %8-11r, %16-19r, %Ssbc%20's%c.w %8-11r, %16-19r, %Ssub%20's%c.w %8-11r, %16-19r, %Srsb%20's%c %8-11r, %16-19r, %Sstrex%c %8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]and%20's%c.w %8-11r, %16-19r, %Mbic%20's%c.w %8-11r, %16-19r, %Morr%20's%c.w %8-11r, %16-19r, %Morn%20's%c %8-11r, %16-19r, %Meor%20's%c.w %8-11r, %16-19r, %Madd%20's%c.w %8-11r, %16-19r, %Madc%20's%c.w %8-11r, %16-19r, %Msbc%20's%c.w %8-11r, %16-19r, %Msub%20's%c.w %8-11r, %16-19r, %Mrsb%20's%c %8-11r, %16-19r, %Mstmia%c.w %16-19r%21'!, %mldmia%c.w %16-19r%21'!, %mstmdb%c %16-19r%21'!, %mldmdb%c %16-19r%21'!, %mstrd%c %12-15r, %8-11r, [%16-19r]ldrd%c %12-15r, %8-11r, [%16-19r]strd%c %12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%Lldrd%c %12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%Lstrd%c %12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%Lldrd%c %12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%Lstr%w%c.w %12-15r, %aldr%w%c.w %12-15r, %aundefined (bcc, cond=0xF)undefined (bcc, cond=0xE)b%22-25c.w %b%Xb%c.w %B%xblx%c %B%xbl%c %B%x-PP `/@@@``p@ @@@@@@@@@@@@@@@@@@@@@L@Dp@Q@AP@`0p p/PO/?O_@ @P` @P` @P` @P` @P` @P`p @`@ 0@P 0@Po Oopp`POop 0@P`0 0@ `  @ @`@`@ @`@`@PPP`ppp@@eqnecsccmiplvsvchilsgeltgtleallsllsrasrrorreg-names-rawSelect raw register namesr0r1r2r3r4r5r6r7r8r9r10r11r12r13r14r15reg-names-gccSelect register names used by GCCslfpipsplrpcreg-names-stdSelect register names used in ARM's ISA documentationforce-thumbAssume all insns are Thumb insnsno-force-thumbExamine preceding label to determine an insn's typereg-names-apcsSelect register names used in the APCSa1a2a3a4v1v2v3v4v5v6reg-names-atpcsSelect register names used in the ATPCSv7v8IPSPLRPCreg-names-special-atpcsSelect special register names used in the ATPCSWRSBSLFPcoproc=(cde|generic)Enable CDE extensions for coprocessor N spacebhwdbusbcbsshushchsswuswcwssdusdcdsswr0wr1wr2wr3wr4wr5wr6wr7wr8wr9wr10wr11wr12wr13wr14wr15wcidwconwcssfwcasfreservedwcgr0wcgr1wcgr2wcgr3tttttttetteeteteteeeeeeeteettetete8163264/export/home/pmunts/src/muntsos/toolchain/crosstool/build.d/aarch64-muntsos-linux-gnu/src/gdb/opcodes/arm-dis.cvpt_block_state.num_pred_insn >= 1%s, rrx%s #%d @ -[#%s%lu]]!], %lu#%ld @ 0x%.2lx#%lu @ 0x%.4lx#%.7g @ 0x%.8lx#0x%.8lx%.8lx??illegal sizesize equals zerosize equals twosize equals threesize <= 1size not equal to 0size not equal to 2size not equal to 3not unsigned and size = zeronot unsigned and size = onenot unsignedinvalid imm6fsi = 0 and invalid imm6bad size with op2 = 2 and op1 = 0 or 1unsigned with op2 = 0 and op1 = 0 or 1op field equal 0 and bad cmodeexchange and unsigned together undefined instruction: %smve instruction in it blockcondition bits, fca = 0 and fcb = 1use of r13 (sp)use of r15 (pc)start register block > r4start register block > r6use of r13 and write backsame vector register used for destination and other operanduse of offset scaledsame general-purpose register used for both operandsuse of identical q registers and size = 1 @ %s: %s{q%ld}anpmxzf16.s16s16.f16f16.u16u16.f16f32.s32s32.f32f32.u32u32.f32f16.f32f32.f16902700180i32i16i8i64f32p8p16%u%%!]%s#-0, {%s%d @ d%d-%c%d-d%ld%ld @ 0x%08x %c%u.%01u @ 0x%08x %c%u.%03u @ 0x%08x %c%u.%07u0x%lx%c%d#%s%dlsl INVALID @ 0x%lx, %s], %sAPSR_nzcvs%up%u,}, [ :d%d[%d]d%d[] :-#%uuxtw suzri124s%ld0x%08lxCPSRR8_usrR9_usrR10_usrR11_usrR12_usrSP_usrLR_usrR8_fiqR9_fiqR10_fiqR11_fiqR12_fiqSP_fiqLR_fiqLR_irqSP_irqLR_svcSP_svcLR_abtSP_abtLR_undSP_undLR_monSP_monELR_hypSP_hypSPSRSPSR_fiqSPSR_irqSPSR_svcSPSR_abtSPSR_undSPSR_monSPSR_hypsystldishishstishldununstnshldoshoshstoshld @ from Armv4T onwards @ p-variant is OBSOLETE[%s, #%d]%s, #%d, {%d}(UNDEF: %lu)%cPSR_fc @ IMB @ IMBRange%01lx(invalid: %lu:%lu) @ instruction: %08x @ unpredictable branch in IT block @ unpredictable 0x%04lx @ instruction: %04xAPSRIAPSREAPSRPSRIPSREPSRIEPSRMSPPSPMSPLIMPSPLIMPRIMASKBASEPRIBASEPRI_MAXFAULTMASKCONTROLPAC_KEY_P_0PAC_KEY_P_1PAC_KEY_P_2PAC_KEY_P_3PAC_KEY_U_0PAC_KEY_U_1PAC_KEY_U_2PAC_KEY_U_3MSP_NSPSP_NSMSPLIM_NSPSPLIM_NSPRIMASK_NSBASEPRI_NSFAULTMASK_NSCONTROL_NSSP_NSPAC_KEY_P_0_NSPAC_KEY_P_1_NSPAC_KEY_P_2_NSPAC_KEY_P_3_NSPAC_KEY_U_0_NSPAC_KEY_U_1_NSPAC_KEY_U_2_NSPAC_KEY_U_3_NSlsr asr ror , ]#%c%ush(invalid: %s)%x.byte0x%02lx.short.word__tagsym$$reg-names-unrecognised register name set: %scoproccde coprocessor not between 0-7: %scoproc must have an argument: %sgenericcdeCDEcoprocN argument takes options "generic", "cde", or "CDE": %sunrecognised disassembler option: %s The following ARM specific disassembler options are supported for use with the -M switch: %s%*c %s mark_inside_vpt_block   6' 5##\#|GCC: (crosstool-NG 1.28.0) 15.2.0zRx <A M8(AHPADh<AM@A0N,AIA0cDA h <AM$A oDhAXdAP mA@\AU(AHA^\A0UAP m 0 A` B <TxAtlA8A&%LhAp XA`A@XA@4AP T A@tdAp WdA@WA0a A@`Ah AP d,AP LA ~l&A<; @A0N@A0NAP >@A A0/ ,AB]PA9l`AVA('`AAp'A>= A@c A0_@AP `A` A@~pA0ZAP }A` pA T AS@tA [`(A HA h lA@BW <<(+d<|<P@iil@-ExwPB: }JX 7`67 :? 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