{ BeagleBone Analog Input Test                                                }

{ Copyright (C)2017-2024, Philip Munts dba Munts Technologies.                }
{                                                                             }
{ Redistribution and use in source and binary forms, with or without          }
{ modification, are permitted provided that the following conditions are met: }
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{   this list of conditions and the following disclaimer.                     }
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{ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" }
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{ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE  }
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{ POSSIBILITY OF SUCH DAMAGE.                                                 }

PROGRAM test_beaglebone_adc(input, output);

USES
  ADC,
  ADC_libsimpleio,
  BeagleBone,
  SysUtils,
  Voltage;

VAR
  inputs : ARRAY [0 .. 6] OF Voltage.Input;
  i      : Voltage.Input;

BEGIN
  Writeln;
  Writeln('BeagleBone Analog Input Test');
  Writeln;

  { Create analog input objects }

  inputs[0] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN0, 12), 1.8);
  inputs[1] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN1, 12), 1.8);
  inputs[2] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN2, 12), 1.8);
  inputs[3] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN3, 12), 1.8);
  inputs[4] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN4, 12), 1.8);
  inputs[5] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN5, 12), 1.8);
  inputs[6] := Voltage.InputClass.Create(ADC_libsimpleio.InputSubclass.Create(AIN6, 12), 1.8);

  { Display analog samples }

  Writeln('Press CONTROL-C to exit.');
  Writeln;

  REPEAT
    FOR i IN inputs DO
      Write(i.Read : 6 : 2);

    Writeln;

    Sleep(2000);
  UNTIL False;
END.