STMicroelectronics STM32F4 Cortex-M4 ARM Microcontroller Framework

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`CMSIS/`	`512`	`Jan 11 02:20:19 2018`
`Makefile`	`1529`	`Nov 25 08:57:47 2018`
`README.txt`	`2810`	`Mar 15 05:15:59 2017`
`adc.c`	`7545`	`Nov 25 08:57:47 2018`
`boards.mk`	`5225`	`Apr 6 06:46:45 2019`
`cpu.c`	`3373`	`Jan 11 02:20:19 2018`
`cpu.h`	`1558`	`Jan 11 02:20:19 2018`
`gpio.c`	`3307`	`Jan 11 02:20:19 2018`
`gpio.h`	`25599`	`Jan 11 02:20:19 2018`
`serial.c`	`26203`	`Mar 26 06:23:45 2019`
`stm32f4.flashocd`	`1813`	`Jan 11 02:20:19 2018`
`stm32f4.mk`	`1941`	`Jan 11 02:20:19 2018`
`stm32f4.openocd`	`1471`	`Jan 11 02:20:19 2018`
`stm32f405rg.S`	`6928`	`Jan 25 11:01:21 2021`
`stm32f405rg.debugjlink`	`1527`	`Jan 11 02:20:19 2018`
`stm32f405rg.ld`	`2991`	`Jan 11 02:20:19 2018`
`stm32f407vg.S`	`6928`	`Jan 25 11:01:21 2021`
`stm32f407vg.debugjlink`	`1527`	`Jan 11 02:20:19 2018`
`stm32f407vg.ld`	`2991`	`Jan 11 02:20:19 2018`
`stm32f411re.S`	`6563`	`Jan 25 11:01:21 2021`
`stm32f411re.debugjlink`	`1498`	`Jan 11 02:20:19 2018`
`stm32f411re.ld`	`2885`	`Jan 11 02:20:19 2018`
`stm32f415rg.S`	`6928`	`Jan 25 11:01:21 2021`
`stm32f415rg.debugjlink`	`1527`	`Jan 11 02:20:19 2018`
`stm32f415rg.ld`	`2991`	`Jan 11 02:20:19 2018`
`stm32f446re.S`	`6563`	`Jan 25 11:01:21 2021`
`stm32f446re.debugjlink`	`1498`	`Feb 10 12:25:49 2018`
`stm32f446re.ld`	`2885`	`Feb 10 12:25:49 2018`

Credits

The C run time startup code stm32f4xxxx.S and linker scripts stm32f4xxxx.ld were written by myself based on various examples on the Internet and in The Definitive Guide to the ARM Cortex-M3.

The CMSIS library came from STMicroelectronics, extracted from the STM32CubeF4 software package.

Other files are original works by myself.

Memory Map (STM32F407VG)

Code Flash:	`0x00000000 to 0x000FFFFF`	1024 KB
Data RAM:	`0x20000000 to 0x2001FFFF`	128 KB
CCM RAM:	`0x10000000 to 0x1000FFFF`	64 KB

The STM32F4 microcontrollers can have any of code flash at 0x08000000, system ROM (boot loader) at 0x1FFF0000, or data RAM at 0x20000000 mapped to address 0x00000000, depending on the BOOT0 and BOOT1 pins. This framework assumes BOOT0 is strapped low, mapping code flash to 0x00000000.

This framework assumes a single stack for both thread and handler modes, using MSP (Main Stack Pointer) at the top of RAM. The C heap is placed at the end of BSS data.

Note: CCM RAM is inaccessible to peripherals (DMA/Ethernet/USB).

Other Devices

This framework may be used for other devices in the STM32F4 family, provided the following files are modified:

`stm32f4xxxx.ld`	The RAM and ROM sizes must match the device.
`stm32f4xxxx.S`	The interrupt vector table must match the device.
`stm32f4xxxx.debugjlink`	The memory regions reported to GDB must match the device.

Test Platform

This framework is validated on the following STM32F4xx development boards:

Tested on 10 June 2015 with gcc 4.9.2.

Questions or comments to Philip Munts phil@munts.net

I am available for custom system development (hardware and software) of products using the STM32F4 or other microcontrollers.