NXP (nee Philips) LPC17xx ARM Cortex-M3 Microcontroller Framework

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`CMSIS/`	`512`	`Jan 11 02:20:19 2018`
`Makefile`	`1419`	`Jan 11 02:20:19 2018`
`README.txt`	`1792`	`Mar 15 05:15:58 2017`
`boards.mk`	`2237`	`Apr 6 06:46:45 2019`
`cpu.c`	`1285`	`Jan 11 02:20:19 2018`
`cpu.h`	`1551`	`Jan 11 02:20:19 2018`
`gpio.c`	`2623`	`Jan 11 02:20:19 2018`
`gpio.h`	`28376`	`Jan 11 02:20:19 2018`
`lpc17xx.S`	`6374`	`Jan 25 11:01:21 2021`
`lpc17xx.debugjlink`	`1498`	`Jan 11 02:20:19 2018`
`lpc17xx.flashocd`	`1811`	`Jan 11 02:20:19 2018`
`lpc17xx.ld`	`3069`	`Jan 11 02:20:19 2018`
`lpc17xx.mk`	`1765`	`Jan 11 02:20:19 2018`
`lpc17xx.openocd`	`1474`	`Jan 11 02:20:19 2018`
`serial.c`	`6458`	`Mar 26 06:23:45 2019`

Credits

The C run time startup code lpc17xx.S and linker script lpc17xx.ld were written by myself based on various examples on the Internet and in The Definitive Guide to the ARM Cortex-M3.

The CMSIS library came from NXP, with some minor customization by myself.

Other files are original works by myself.

Memory Map (LPC1768)

Code Flash:	`0x00000000 to 0x0007FFFF`	512 KB
Data RAM:	`0x10000000 to 0x10007FFF`	32 KB

Other Devices

This framework may be used for other devices in the NXP LPC17xx family, provided the following files are modified:

`lpc17xx.ld`	The RAM and ROM sizes must match the device.
`lpc17xx.S`	The interrupt vector table must match the device.
`lpc17xx.debugjlink`	The memory regions reported to GDB must match the device.

Test Platform

This framework is validated on the following LPC17xx development boards:

Tested on 10 June 2015 with gcc 4.9.2.

Questions or comments to Philip Munts phil@munts.net

I am available for custom system development (hardware and software) of products using the LPC17xx or other microcontrollers.