Index of /arm-mcu/gcc/lpc11xx

      Name                    Last modified       Size  

[DIR] Parent Directory 15-Mar-2017 12:15 - [DIR] CMSIS/ 11-Jan-2018 10:20 - [   ] LPC1114FN28.S 11-Jan-2018 10:20 6k [   ] LPC1114FN28.debugjlink 11-Jan-2018 10:20 1k [   ] LPC1114FN28.ld 11-Jan-2018 10:20 3k [   ] Makefile 11-Jan-2018 10:20 1k [TXT] README.txt 15-Mar-2017 12:15 2k [TXT] adc.c 11-Jan-2018 10:20 4k [TXT] 11-Jan-2018 10:20 2k [TXT] cpu.c 11-Jan-2018 10:20 1k [TXT] cpu.h 11-Jan-2018 10:20 2k [TXT] gpio.c 11-Jan-2018 10:20 10k [TXT] gpio.h 11-Jan-2018 10:20 3k [TXT] i2c.c 11-Jan-2018 10:20 4k [TXT] 11-Jan-2018 10:20 2k [TXT] pwm.c 11-Jan-2018 10:20 9k [TXT] serial.c 26-Mar-2019 13:23 5k [TXT] spi.c 11-Jan-2018 10:20 2k [TXT] timer.c 26-Jun-2019 18:40 7k [TXT] timer.h 11-Jan-2018 10:20 3k

NXP (nee Philips) LPC11xx ARM Cortex-M0 Microcontroller Framework


The C run time startup code lpc11xxxx.S and linker scripts lpc11xxxx.ld were written by myself based on various examples on the Internet and in The Definitive Guide to the ARM Cortex-M3.

The CMSIS library came from NXP, with some minor customization by myself.

Other files are original works by myself.

Memory Map (LPC1114/102)

Code Flash: 0x00000000 to 0x00007FFF 32 KB
Data RAM: 0x10000000 to 0x10000FFF 4 KB

Other Devices

This framework may be used for other devices in the NXP LPC11xx family, provided the following files are modified:

lpc11xxxx.ld The RAM and ROM sizes must match the device.
lpc11xxxx.S The interrupt vector table must match the device.
lpc11xxxx.debugjlink The memory regions reported to GDB must match the device.

Test Platform

This framework is validated on the following LPC11x development boards:

Tested on 9 August 2013 with gcc 4.8.1.

Questions or comments to Philip Munts

I am available for custom system development (hardware and software) of products using the LPC11xx or other microcontrollers.