NXP (nee Philips) LPC11xx ARM Cortex-M0 Microcontroller Framework

../
CMSIS/  512Jan 11 02:20:19 2018
LPC1114FN28.S  6489Jan 11 02:20:19 2018
LPC1114FN28.debugjlink  1498Jan 11 02:20:19 2018
LPC1114FN28.ld  3018Jan 11 02:20:19 2018
Makefile  1422Jan 11 02:20:19 2018
README.html  2188Mar 15 05:15:58 2017
README.txt  1945Mar 15 05:15:58 2017
adc.c  3700Jan 11 02:20:19 2018
boards.mk  1662Jan 11 02:20:19 2018
cpu.c  1285Jan 11 02:20:19 2018
cpu.h  1810Jan 11 02:20:19 2018
gpio.c  10163Jan 11 02:20:19 2018
gpio.h  2982Jan 11 02:20:19 2018
i2c.c  4362Jan 11 02:20:19 2018
lpc11xx.mk  1751Jan 11 02:20:19 2018
pwm.c  8743Jan 11 02:20:19 2018
serial.c  5414Mar 26 06:23:45 2019
spi.c  2521Jan 11 02:20:19 2018
timer.c  6973Jun 26 11:40:49 2019
timer.h  2706Jan 11 02:20:19 2018

Credits

The C run time startup code lpc11xxxx.S and linker scripts lpc11xxxx.ld were written by myself based on various examples on the Internet and in The Definitive Guide to the ARM Cortex-M3.

The CMSIS library came from NXP, with some minor customization by myself.

Other files are original works by myself.

Memory Map (LPC1114/102)

Code Flash: 0x00000000 to 0x00007FFF 32 KB
Data RAM: 0x10000000 to 0x10000FFF 4 KB

Other Devices

This framework may be used for other devices in the NXP LPC11xx family, provided the following files are modified:

lpc11xxxx.ld The RAM and ROM sizes must match the device.
lpc11xxxx.S The interrupt vector table must match the device.
lpc11xxxx.debugjlink The memory regions reported to GDB must match the device.

Test Platform

This framework is validated on the following LPC11x development boards:

Tested on 9 August 2013 with gcc 4.8.1.


Questions or comments to Philip Munts phil@munts.net

I am available for custom system development (hardware and software) of products using the LPC11xx or other microcontrollers.